RealTime Floorplan Compiler Reduces Time to Generate a Floorplan from 4-6 Weeks to a Couple Days

One of the most timing consuming tasks in the implementation phase of SoC & ASIC design is generating an initial floorplan. Oasys RealTime Floorplan Compiler streamlines this process by compiling a floorplan directly from RTL that meets timing, power, area and physical constraints to feed forward as initial guidance to place & route teams.

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EDA Consortium (EDAC) Votes Oasys Design “The Hottest EDA Startup”

At the recent EDA Consortium Annual CEO Forecast and Industry Vision event held on March 14, 2013, members were asked to vote for the “Hottest EDA Startup”. The vendor receiving the most votes was Oasys Design Systems. We appreciate the recognition and honor bestowed upon us by our peers in the EDA and Semiconductor IP industry and will do everything possible to fulfill their expectations!