RealTime Floorplan Compiler eliminates up to 80% of the iterations between synthesis and place & route teams required to generate an optimized floorplan reducing schedules by about a month

One of the most timing consuming tasks in the implementation phase of SoC & ASIC design is generating an initial floorplan.  Oasys RealTime Floorplan Compiler streamlines this process by compiling a data flow driven floorplan directly from RTL that concurrently optimizes for timing, power, area and physical constraints to feed forward as initial guidance to place & route teams.  Click on the Products tab above to learn more.