Sandeep Bhatia’s article for Tech Design Forum is finally online. The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what Read more…

Paul’s predictions for 2012 are now up at EEtimes here and here. First is about how power is the biggest problem and will continue to be: The big issue in 2012 will continue to be power. The big challenge in designing an SoC is whether the entire chip can be Read more…

For the third year in a row, RealTime Designer has made it to John Cooley’s top 5 tools that users thought were “hot” at DAC. As one (anonymous) engineer says: “Oasys clearly has the tool for next generation, very large scale synthesis. I push the purple button every day and Read more…