Last week I met Jay Singh of Plato Networks. He was one of the earliest users of Oasys RealTime Designer and I wanted to find out what his experience was. Jay got involved with Oasys early on, before the tool was mature, and has given a lot of feedback over the last year and a half.
A bit of background on Plato. They are building 10 gigabit PHY solutions for the next generation of data centers. Big complex chips with enormous amounts of interconnect.
Jay thinks that it’s great that RealTime Designer is so fast but that is not the most valuable aspect of it for him. The biggest strength is the consistency of the results from synthesis with what comes out after place and route. But it is fast. On difficult blocks he found that it was 20x to 60x the speed of traditional synthesis tools.
If he provides a floorplan, then he reckons the results are 100% predictable. What RealTime Designer says is what you will get. Furthermore, you’ll get it faster since the netlist seems to be very friendly to the place and route tools and designs seem to go through physical flow much more quickly and smoothly. Speed improvements of up to 3X have been observed in the existing backend flow, using same set of scripts, simply by swapping traditional tool netlist with the RealTime Designer generated one. You simply don’t get that consistency with other synthesis tools. With them, after place and route the results may be better or they may be worse than predicted. The prediction simply isn’t very good. To cap it off, in some cases the blocks are 20% smaller than with traditional synthesis.
One interesting thing I didn’t know is that RealTime Designer sometimes creates more instances than traditional synthesis, which typically works hard to reduce instance count. For example Jay saw 2.5X more instances in a connectivity-intensive design and despite that the backend physical implementation had more than 2X speed improvement over traditional synthesis.
Why is this? Oasys knows timing and placement from the very beginning. Traditional synthesis tools simply try and minimize the instance count. This used to be a sensible thing to do but now that interconnect is as a big a problem as cell area that doesn’t seem to be true any more. To take a simple example: if a signal is used in two places on a chip, and its inverse is also needed in both places, traditional synthesis tends to create one inverter and then run the inverted signal to both places that it is needed. If those two points are close together then this is a good decision. If they are far apart, it makes more sense to put a small inverter at both points, which pushes up the instance count but removes a long wire and reduces congestion. Decisions like this about how to structure the netlist can only be taken when the RTL, the placement and the timing are all available at once, which is just the approach taken by RealTime Designer.
His view of adoption of RealTime Designer is that the scripts are very simple. It is easy to use and the commands are very consistent with other synthesis vendors so there is a shallow learning curve. In fact, because RealTime Designer just takes the entire design and synthesizes it, there are only a few commands that get used much. Cross probing between schematic and RTL source works really well.
It runs perfectly in batch mode and Jay likes to set it up to run a whole matrix of different performance tradeoffs overnight since it is so fast. In effect, instead of using intellect to work out how to tweak the performance, just burn up lots of computer time (cheap) and do 20 runs. It has the features of other synthesis tools but Oasys have made it simpler.