What do genomes have to do with chip synthesis? When Oasys started, they needed a name for the RTL partitions that are the heart of the chip synthesis approach. They decided to call them genomes since in a way they embody the DNA of the design. Of course to start with, this was just an internal name as they developed the code. When they started to present the product to potential customers, they continued to use the name genome since it is catchy. However, that turned out to be a mistake. Everyone focused on the name, since it is catchy, and wanted to know how it related to real genomes, and precisely what was in a genome and so on, and got completely distracted from the results of the chip synthesis process.
EDA tends to be like that. Designers don’t just want to know how good the results are, they want to understand the internals of the tool to convince themselves that the tool works since actually doing an evaluation is too expensive. It’s as if when an EDA engineer goes to buy a car, instead of taking a test-drive, they take off the cylinder head and check the camshaft angles.
Anyway, the name genome is no longer used and they are just referred to as RTL partitions, which is less catchy but sufficiently descriptive not to be distracting. So what are these RTL partitions aka genomes?
Once the RTL has been read into Oasys RealTime Designer, it is divided up based on connectivity into smaller blocks that will eventually be implemented as a bunch of gates. The partitions are small enough that they won’t contain any long wires, which would lead to high variability in timing, but large enough to have implementations with potentially different space-time tradeoffs. Each partition is largely independent of the others. Of course the timing of all the other partitions is required to be able to time the whole chip, but the detailed internals of every partition are not required at the same time. Since it is no longer necessary to look at the whole chip at the gate-level at the same time, then the memory requirements are hugely reduced. The old approach to synthesis does all the optimization at the gate-level and requires a huge amount of data for every gate to be around in memory simultaneously, which is why it has such a low ceiling on the size of block that can be efficiently synthesized.
The RTL partition approach is the main reason that Oasys RealTime Designer can be so fast and so effective. By operating at a higher level, it intelligently synthesizes and times the design one partition at a time. Then, until timing is met, it re-synthesizes, re-places (and updates the global routes) and perhaps re-partitions parts of the design until the constraints are met.