What do genomes have to do with chip synthesis? When Oasys started, they needed a name for the RTL partitions that are the heart of the chip synthesis approach. They decided to call them genomes since in a way they embody the DNA of the design. Of course to start with, this was just an internal name as they developed the code. When they started to present the product to potential customers, they continued to use the name genome since it is catchy. However, that turned out to be a mistake. Everyone focused on the name, since it is catchy, and wanted to know how it related to real genomes, and precisely what was in a genome and so on, and got completely distracted from the results of the chip synthesis process.

EDA tends to be like that. Designers don’t just want to know how good the results are, they want to understand the internals of the tool to convince themselves that the tool works since actually doing an evaluation is too expensive. It’s as if when an EDA engineer goes to buy a car, instead of taking a test-drive, they take off the cylinder head and check the camshaft angles.

Anyway, the name genome is no longer used and they are just referred to as RTL partitions, which is less catchy but sufficiently descriptive not to be distracting. So what are these RTL partitions aka genomes?

Once the RTL has been read into Oasys RealTime Designer, it is divided up based on connectivity into smaller blocks that will eventually be implemented as a bunch of gates. The partitions are small enough that they won’t contain any long wires, which would lead to high variability in timing, but large enough to have implementations with potentially different space-time tradeoffs. Each partition is largely independent of the others. Of course the timing of all the other partitions is required to be able to time the whole chip, but the detailed internals of every partition are not required at the same time. Since it is no longer necessary to look at the whole chip at the gate-level at the same time, then the memory requirements are hugely reduced. The old approach to synthesis does all the optimization at the gate-level and requires a huge amount of data for every gate to be around in memory simultaneously, which is why it has such a low ceiling on the size of block that can be efficiently synthesized.

The RTL partition approach is the main reason that Oasys RealTime Designer can be so fast and so effective. By operating at a higher level, it intelligently synthesizes and times the design one partition at a time. Then, until timing is met, it re-synthesizes, re-places (and updates the global routes) and perhaps re-partitions parts of the design until the constraints are met.

By Sanjiv Kaul, Executive Chairmain, Oasys Design Systems, Inc.

Several people used to ask me questions about why I am involved with Oasys both as an investor and an active Executive Chairman. Why did you invest in Oasys? Isn’t EDA in trouble? Aren’t EDA startups having a hard time? Even if your technology is good, isn’t it very hard for a startup to build a business in EDA?

All good questions. Investing in EDA can be hazardous to your wallet! The Oasys story is still being written but I thought I would share my insights. Monday morning quarterbacks are always right, but it is the analysts who can read the game while it is being played that are worth listening to. So let me try and put my mouth where my money is.

There is a reason why so few EDA startups are successful. Too many EDA startups are launched with a quick acquisition in mind. Often they are better implementations of key features in an existing design platform. Such start ups typically have a hard time making it. Not only is integrating that product into existing flows hard but typically the large companies focus resources to close the gap especially if the startup is getting traction. There has to be a sustainable advantage that is meaningful to customers for a business to be successful

When Paul, Harm and Johnson first pitched the Oasys idea to me I was immediately attracted to it. There were several reasons:

1. Oasys was trying to address a real customer pain. Current synthesis technology was getting increasingly inadequate for design teams doing large chips. The run times were too long, managing constraints for 100s of blocks too cumbersome, and the results coming out of synthesis were not very meaningful given the big impact of floorplans and physical implementation.. As a result the timing closure problem was increasingly a back end issue and synthesis was becoming commodity. Most high end teams have all the different synthesis solutions available to them and use the output of whichever one delivers the best results after P&R.

2. The Oasys solution was going to be a complete platform. That meant it would be possible to build a sustainable advantage over the competition because the product depended on standards to interface into design flows.

3. What the Oasys founders wanted to do was pretty audacious. But that is what it takes to be successful as a startup. In EDA if you don’t have a 10X advantage at least, it is hard to break through the all you can eat, preferred vendor deals that the major EDA vendors like to do with their major customers. Customers will not switch in a big way to new technology from a startup unless they see a sustainable lead. If Oasys accomplished what it wanted to do, then Oasys would have a 4-5 year lead over the incumbents. Synopsys was quickly able to close the technical gap with Ambit and so it disappeared from the market. With RC Compiler, it has taken Synopsys longer and that is why RC has decent market share.

4. The Oasys solution is so different from existing synthesis solutions that it is a new product category: Chip Synthesis.

5. The founders felt they could develop the product with a limited investment. That was key, given that EDA had fallen out of favor with Sand Hill Road.

6. There was a large addressable market. If you don’t see a path to a $100M business for a start up then you should not do it in my opinion. It is as hard to build a $10M company as it is to build a $100M company. But your chances of success are much better with the $100M play.

After I joined the initial angel investors, Paul and his team went away and worked on the technology. They came back after two and a half years and said that they thought they had done it! Oasys asked me to join the Board to help drive the company to the next level. I was excited about the technology but also a little skeptical. How would the product hold up on different kinds of designs? Was the product full featured? Could customers deploy this product? Too many EDA products have too small a sweet spot. They do well on the initial carefully selected benchmarks but falter on different design styles.

So we spent the next two years validating the Oasys solution on different design types and converging with customers on needed functionality. The key was to deliver the best starting point for physical implementation. That meant producing placed netlists that delivered targeted QoR after P&R. That meant going smoothly through all the popular P&R systems . That meant helping design teams to converge to their floorplan as early in the design process as possible.

It was only after carefully proving out the product that we announced the company and the product. Oasys has a long road ahead. But as our mothers used to say, “A task well begun, is half done”!