Last weekend I talked to Yoshio Inoue of Renesas. It was a convenient 3pm on a Friday afternoon for me but it was 7am on Saturday morning in Japan, so definitely going beyond the call of duty.
Renesas, in particular Inoue-san and his team, was one of the earliest companies to use Oasys RealTime Designer. They have been working with Oasys for about two and a half years. He considers that it is the most advanced synthesis technology and has the potential to start to change the usage model and is the missing link to drive chip implementation up to a higher level. Their experience is that it is 100 times as fast as other synthesis tools. For example, on one 22 million gate design, also including 500 memories, the entire chip is synthesized from top level RTL to placed gates in about an hour. He says it produces better results than other synthesis tools in a fraction of the time.
Of course in the early days there were the usual teething problems of any immature tool such as consistency issues between placed gates from RealTime Designer and the detailed timing after final place and route.
Inoue-san plans to transition to RealTime Designer for final synthesis but right now doesn’t have the budget to get all the tools he needs. It is no secret, as he put it, that “currently Japanese business is not very good, also Renesas too.”
Today, it is their most experienced designers who are using RealTime Designer. They have used it on designs that are simply too difficult to do bottom up with traditional synthesis tools. The great thing about doing design top down is that you can see the global nets, which are the ones that typically cause problems with closing timing in a bottom-up approach. This is very difficult with Design Compiler (mainly because the speed is so slow even though eventually results may be acceptable).
Historically Renesas has been very strong on floorplan and, in particular, getting to a good floorplan early. It is too late to wait until physical design begins to create a floorplan, but front-end designers are simply not very good at this. There is a discrepancy between the mindsets of front-end and back-end designers which makes this a challenge. Front-end designers simply do not understand physical constraints like I/O and RAM placement and so sometimes produce floorplans that are garbage but without any tools to make this clear. RealTime Designer, which can synthesize the whole chip into a given floorplan helps make this problem less severe by exposing poor floorplans early so that they can be altered when it is still early and easy to make such changes.
Looking to the future, Inoue-san sees RealTime Designer as a key piece of the puzzle of driving chip design up to a higher level, the other pieces being high-level synthesis (HLS) and floorplanning that works at that level.
Inoue-san wants to be able to regard RTL simply as an “intermediate code” that is generated from higher-level tools. They are also a lead customer for Cadence’s CtoSilicon HLS product. He wants move away from treating RTL as something a person writes, to something that is only written by other tools. But this approach only work if there is a tool that can consume the entire block or the entire chip, and reduce it to place and timed gates fast enough that the designers can get the feedback they need to make design tradeoffs. Oasys RealTime Designer is this missing link, able to take the entire chip and turn it into placed gates in very short timeframes.
Oasys is then the tool that consumes that RTL. However there are weaknesses in the approach today since c2silicon is not good enough for control which means that some RTL still has to be created by hand. It is like programming in the 70s where high-level languages could be used much of the time, but sometimes it was necessary to write critical pieces in assembly code.
Going forward, Inoue-san reckons that either high-level synthesis needs to get good enough to handle the whole design, or Oasys needs to move up and support high-level synthesis directly in the future, or perhaps some API-based combination of the two synthesis levels. That is what is needed to be able to completely hide RTL from a design point of view. RealTime Designer is the only tool that can form the foundation for that methodology transition which will drive up the level of abstraction used by designers to C/SystemC and potentially create a disruptive step-function in designer productivity.