Oasys announced a new version 9.3 of RealTime Designer with two main new features. The first is support for VHDL.
VHDL is, of course, one of the two main hardware description languages dating back to the 1980s. The history of Verilog and VHDL is quite interesting. Verilog was originally created by Gateway Design Automation. Gateway was subsequently acquired by Cadence for what seemed like a very high valuation at the time, although of course it has probably been one of the most successful acquisitions Cadence did when you think of the sales of Verilog that they have made over the intervening years. VHDL, which is actually one of those nested acronyms since it stood for VHSIC Hardware Description Language, with VHSIC further parsed down into Very High Speed Integrated Circuit. The VHSIC program was run by the US DoD and VHDL looked for a time that it might become the dominant standard, since Verilog was a proprietary language owned by Cadence.
But Cadence opened Verilog up and let other people participate in driving the language standard. As Gordon Bell once said, the only justification for VHDL was to force Cadence to put Verilog into the public domain. But having two languages has been a major cost to the EDA industry for very little gain. VHDL was a very powerful language but in many ways was less practical than Verilog. For instance, you could define your own values for any signal. But that meant that gates from one library wouldn’t necessarily interact properly with gates from another library (sounds like some of the problems with TLM models in SystemC that are finally being resolved). So that required a new standard, VITAL, so that gate-level signals were standardized. The richness of VHDL abstractions meant that it was and is used for some of the most complex communication chips. Model Technology (now part of Mentor) had probably the best VHDL simulator that they sold cheaply, and that helped to make VHDL more standard in the FPGA market than Verilog. Despite the fact that a Verilog simulator is easier to write than a VHDL simulator, it sold for a higher price for years. This has led to an odd phenomenon where some of the most advanced chips are done in VHDL, and many of the simpler ones.
Anyway, the dual language environment (and, of course, SystemVerilog has arrived to make a third) continues to exist, and now VHDL users can take advantage of Oasys’s Chip Synthesis technology with its huge capacity and very accurate timing prediction. Of course Oasys is focused on the biggest designs (not that you can’t use it for small ones) so it now addresses these large VHDL designs.
The second feature is multi-mode sythesis. Often designs have more than one mode of operation, such as a test mode for testing the chip and a normal operational mode. Years ago people didn’t worry too much about the test mode and would assume it would “just work.” But in modern processes and the modern speeds for testing that approach isn’t very effective. The synthesis tool needs to take both sets of constraints into account and ensure that timing constraints are met both in the operational mode (in the system) and the test mode (on the tester during manufacture).