Oasys announced a new version 9.3 of RealTime Designer with two main new features. The first is support for VHDL.

VHDL is, of course, one of the two main hardware description languages dating back to the 1980s. The history of Verilog and VHDL is quite interesting. Verilog was originally created by Gateway Design Automation. Gateway was subsequently acquired by Cadence for what seemed like a very high valuation at the time, although of course it has probably been one of the most successful acquisitions Cadence did when you think of the sales of Verilog that they have made over the intervening years. VHDL, which is actually one of those nested acronyms since it stood for VHSIC Hardware Description Language, with VHSIC further parsed down into Very High Speed Integrated Circuit. The VHSIC program was run by the US DoD and VHDL looked for a time that it might become the dominant standard, since Verilog was a proprietary language owned by Cadence.

But Cadence opened Verilog up and let other people participate in driving the language standard. As Gordon Bell once said, the only justification for VHDL was to force Cadence to put Verilog into the public domain. But having two languages has been a major cost to the EDA industry for very little gain. VHDL was a very powerful language but in many ways was less practical than Verilog. For instance, you could define your own values for any signal. But that meant that gates from one library wouldn’t necessarily interact properly with gates from another library (sounds like some of the problems with TLM models in SystemC that are finally being resolved). So that required a new standard, VITAL, so that gate-level signals were standardized. The richness of VHDL abstractions meant that it was and is used for some of the most complex communication chips. Model Technology (now part of Mentor) had probably the best VHDL simulator that they sold cheaply, and that helped to make VHDL more standard in the FPGA market than Verilog. Despite the fact that a Verilog simulator is easier to write than a VHDL simulator, it sold for a higher price for years. This has led to an odd phenomenon where some of the most advanced chips are done in VHDL, and many of the simpler ones.

Anyway, the dual language environment (and, of course, SystemVerilog has arrived to make a third) continues to exist, and now VHDL users can take advantage of Oasys’s Chip Synthesis technology with its huge capacity and very accurate timing prediction. Of course Oasys is focused on the biggest designs (not that you can’t use it for small ones) so it now addresses these large VHDL designs.

The second feature is multi-mode sythesis. Often designs have more than one mode of operation, such as a test mode for testing the chip and a normal operational mode. Years ago people didn’t worry too much about the test mode and would assume it would “just work.” But in modern processes and the modern speeds for testing that approach isn’t very effective. The synthesis tool needs to take both sets of constraints into account and ensure that timing constraints are met both in the operational mode (in the system) and the test mode (on the tester during manufacture).

Last week was the EDAC Kauffman Award dinner. One minor advantage of being a blogger is that I got invited along as press. Will blog for food. This year’s winner was Professor Randal Bryant, usually just known as Randy Bryant.

I knew of Randy as the inventor of switch level simulation with a tool called MOSSIM. Up until that point, all simulation of semiconductor had been done using Spice type algorithms, worrying about the transfer functions of the transistors. But with the coming of Mead and Conway, computer scientists were starting to want a much simpler model of the world so that they could apply programming techniques to design. Treat transistors as switches that were either on or off and with a unit delay (all transistors turned on and off at the same speed). MOSSIM was the first of these so-called switch level simulators developed in about 1980. Later, the switch model would be enhanced to add timing. Funny now to realize that in the early 1980s IC design was largely done without timing, using Spice for paths that looked like they might be important.

Randy Bryant was also the inventor of BDDs, binary decision diagrams. BDDs are a very efficient representation of combinational logic and are one of the key technologies underlying logic optimization and hence underlying both synthesis and formal verification. The advantage of BDDs is that despite being a fairly compressed representation of the circuit, many logic operations can be done efficiently directly on the BDD, without needing to expand the representation into something less space efficient and then recompress it again afterwards.

Randy first published his ideas in 1986. An amazing fact that came to light at the Kauffman award dinner was that his paper just kept getting more and more citations. Usually a paper generates a flurry of interest soon after publication and then it dies down. But 15 years after publication for most of the early part of this decade, Randy’s paper wasn’t just the most cited paper in EDA, it was the most cited paper in the whole of computer science.

Every synthesis and formal verification tool relies heavily on BDD representation internally. Of course, Oasys Realtime Designer is no different, although since it doesn’t attempt to operate on the entire design simultaneously at netlist level it is perhaps less critical from a memory point of view.

The Kauffman Award is awarded based on the impact that individuals have had on EDA. The ideas in MOSSIM, while very important in the early 1980s have dwindled in importance since simulation has moved up to higher levels. But given that every synthesis and formal verification tool including Oasys Realtime Deisgner relies heavily on BDDs over 20 years after their conception I think that the “impact” is unarguable.

Last week at ICCAD, Jim Hogan and I led an discussion on the megatrends facing electronics and the implications going forward for EDA. Basically we took a leaf out of Scoop Nisker’s book, who when he finished reading the news would sign off with “if you don’t like the news go out and make some of your own.” So we tried to.

The basic premise that we put forward is that end markets are fragmenting, meaning that designs need to be done in smaller volumes, but meanwhile semiconductor technology is pushing design costs so high that few markets are large enough, hundreds of millions of units, to support designing a 45nm chip with its $50M price tag.

As a consequence of this mismatch, designs need to be aggregated in some way so that many systems are constructed out of the same chip(s) so that the chip volumes are high enough to be economical. So FPGAs are likely to become more important going forward, and in fact this is seen in the way that the high end of FPGAs is growing fast.

This has the potential to be good for Oasys since one of the limitations on using FPGAs today are that the synthesis technology is slow and lacks a lot in terms of predicting eventual performance. These FPGAs are huge and complex (including embedded software) and so the old “blow and go” method of simply implementing the design is not adequate for verification going forward.

The big challenge for EDA in general, and this will affect Oasys too, is that the channel required to sell software largely to a couple of dozen large semiconductor companies is not the same as that required to address a much larger market of smaller players. What the correct price points are is also unclear. But electronic design is going in this direction and EDA will have to follow.

Ultimately this is moving towards what I call software signoff, the inversion of the way about thinking about electronic systems. Instead of thinking of a complex SoC with some embedded software, a system is actually a big software system, parts of which need to be accelerated by some type of semiconductor implementation to make them economic (fast enough, low enough power). We don’t yet have the tools today to take complex software and automatically build some parts in gates, assemble IP, assign the software to processors and so on. But that is the direction we need to move in and the type of very fast, very high capacity, very accurate synthesis that Oasys is pioneering will be an important piece of this puzzle.

The mismatch between fragmented end-markets and high costs of design is potentially disruptive and thus an opportunity to change the way that design is done. I return to Yoshihito Kondo of Sony’s call to arms: “We don’t want our engineers writing Verilog, we want them inventing concepts and transferring them into silicon and software using automated processes.” Oasys has important technology to enable this transition.