Rather like suddenly finding Christmas merchandise in the stores in September, Bill Murray over at SCDsource has come out with his list of what to see at DAC. Wait, isn’t DAC 6 weeks away? Has everything already been announced? And just a top 9 list, isn’t 10 the traditional number?
Anyway, happily, Oasys RealTime Designer is on the list, the only synthesis tool to make the cut. Forte and Mentor are there for high-level synthesis but that is a completely different segment, starting from C/SystemC and delivering RTL, just ready to pour straight into RealTime Designer to get an implementation.
Here’s Bill’s description: Courtesy of Oasys, RealTime Designer is the biggest advance in logic synthesis in more than a decade. According to the company, it has the capacity to handle full-chip designs of up to 100 million gates; it is 20 to 100 times faster than mainstream synthesis tools, with better area and timing QoR. How? It operates and optimizes at the chip/RTL level – not merely the block/gate optimization level. A must see.
Synopsys has announced a new release of Design Compiler and Gabe Moretti uses it as a hook to talk about…Oasys. Well, of course, he does talk about Synopsys too but basically argues that Synopsys’s latest announcement is a validation of the Oasys approach. It is never possible to deduce too much from simply reading a press release, but Synopsys doesn’t seem to be announcing anything nearly as radical as the Oasys approach, they have merged a bit more of their placement into DC. They are certainly not doing anything very different at the RTL front-end where the bulk of Oasys’s innovation occurs.
Interestingly, some parts of the article look like something I might have said. Oh wait, there are a couple of paragraphs which are exactly what I said in the white paper!
EDAdesignLine has published Sanjiv’s opinion piece on whether EDA is innovative enough. While I agree with much of what he says there, I think that the ecosystem by which EDA products are created is largely broken. Time and time again the big companies have proved incapable of developing and bringing to market genuinely innovative products. Instead small startups have done this, and then become part of the mainstream through acquisition. That is not happening much any more since EDA is not a growing attractive market for investment. Not everyone can afford to do what the founders of Oasys did and fund the company with sweat equity.
And although each process node brings new problems and bigger chips, each node also brings fewer chips. Although EDA is “strategic” to semiconductor companies in some sense, that’s not how they seem to regard it. It is a cost to be managed in the same was as IT was until the internet came along and suddenly IT was strategic and every company had a CIO. Which semiconductor company has a C-level design methodology officer?