SANTA CLARA, CA–(Marketwire – 06/08/10) – Oasys Design Systems today announced its multi-year strategic licensing agreement with Xilinx for Oasys’ revolutionary Chip Synthesis™ technology.

The companies are not disclosing terms of the agreement or details regarding Xilinx’s long-term plans for implementing the technology for field programmable gate array (FPGA)-based design.

“With programmable chip sizes growing and complexity mounting, it was clear we needed to look at a new generation of synthesis to support the needs of our customers,” says Vin Ratford, Xilinx’s senior vice president of worldwide marketing. “We were immediately impressed with Oasys’ Chip Synthesis technology for its speed, capacity, performance and quality of results.”

Paul van Besouw, Oasys’ president and chief executive officer, adds: “It gives us a great deal of pride that Xilinx has chosen the Oasys technology to address the scaling of solutions for next generation programmable platforms. Oasys currently provides a new generation of implementation platform for ASIC designers. We will continue to focus in this area, and the unique partnership with Xilinx will bring benefits of our revolutionary technology to leading-edge FPGA designers as well.”

RealTime Designer™, based on Oasys’ Chip Synthesis technology, is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs. It synthesizes RTL code to placed gates in a single pass and in a fraction of the time traditional synthesis does. A unique RTL placement feature eliminates unending design closure and iterations between synthesis and layout.

Oasys will demonstrate RealTime Designer at the 47th Design Automation Conference (DAC) in Booth #202 June 14-16 at the Anaheim Convention Center in Anaheim, Calif.

About Oasys Design Systems

Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates. It has attracted the support of legendary EDA leaders and its RealTime Designer™ is in use at leading-edge semiconductor and systems companies worldwide. Follow Oasys on Twitter at: www.twitter.com/OasysDS. Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com

RealTime Designer and Chip Synthesis are trademarks of Oasys Design Systems. All other trademarks and registered trademarks are the property of their respective owners.

One of the challenges with design flows involving high-level synthesis from C, C++ or SystemC is that eventually the exact performance of the design needs to be determined. The built-in metrics in HLS tools are fairly good at determining which of two implementation choices has the highest performance or consumes the least power and can thus guide the exploration of the design space.

However, sooner or later the actual performance or power numbers are required. If a design is to process 30 frames of high-definition video per second then 29 just doesn’t do it. And probably 50 frames per second would be wasting a lot of power and silicon area.

Traditional synthesis followed by placement is a cumbersome way of getting at this data. Chip Synthesis using Oasys RealTime Designer is much smoother, getting to a fully-placed design with accurate performance numbers in a short time. HLS can produce a lot of RTL, tens of thousands of lines, very quickly. Luckily RealTime Designer can easily process this fast to get the data that the system level designer needs to finalize a choice of implementation.

Paul van Besouw from Oasys and Devadas Varma of AutoESL have jointly written an article for Embedded Computing Design on just this topic.

Gabe Moretti has his DAC preview, with his list of companies that attendees should take a look at. We didn’t make the headline list (which is largely Synopsys, Magma, Mentor…) which in some sense will be on any visitors list. After all, no matter what new technology is around, something like 90% of EDA usage is probably the big full-line companies. But Gabe ends up suggesting that “other companies that you should visit include Oasys, making loud noises in physical design.” Hmm, not quite sure that the positioning is quite right there. I thought we were making loud noises in Chip Synthesis. We’ll there’s nearly a week to write a router.

Revolutionary Chip Synthesis to be Implemented into Design Flow

SANTA CLARA, CALIF. –– June 2, 2010 –– Oasys Design Systems today announced that Juniper Networks® has selected RealTime Designer™, a revolutionary new Chip Synthesis™ platform, for the design of its next-generation networking chips.

“After a thorough evaluation, we determined that RealTime Designer offers high-quality results and performs very well in our environment,” said Debashis Basu, vice president for Silicon Development at Juniper Networks. “It is a great tool that fits a very real performance need in today’s EDA market.”

Juniper Networks will incorporate RealTime Designer into its design flow. Terms of the agreement will not be disclosed.

“We are delighted that Juniper Networks has chosen RealTime Designer for its leading-edge chip designs,” remarked Paul van Besouw, Oasys’ president and chief executive officer. “There is an ongoing effort for design teams to scale for next-generation designs, and improve productivity. Juniper’s designers have a superb track record of designing some of the most challenging chips, which has helped to establish Juniper as the industry leader in the networking world.”

RealTime Designer is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs. It features a unique RTL code placement approach that eliminates unending design closure and iterations between synthesis and layout.

About Oasys Design Systems

Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates. It has attracted the support of legendary EDA leaders and its RealTime Designer™ is in use at leading-edge semiconductor and systems companies worldwide. Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com

Every year Gary Smith EDA produces a list of around 20 companies to see at DAC. Oasys is on this years list, yeah! In fact, since the list is put together in booth number order, and Oasys has the lowest booth number of any company on the list, it is the first name on the list. Even better. The list is here.