Defining Chip Synthesis

Chip Design has an article by Paul van Besouw defining Chip Synthesis. Although there are layers of detail like an onion, I think that the key difference from traditional synthesis is that Chip Synthesis does intelligent things with the RTL rather than throwing it away in favor of gates as quickly as possible and never going back.

Instead, Chip Synthesis partitions the RTL and, when constraints are not met, goes back to the RTL to work out a better way of either turning RTL partitions into gates or a better way of repartitioning the RTL.

In addition, Chip Synthesis takes account of placement during RTL synthesis, as opposed to tradtional synthesis, which only considers placement once the design has been reduced to a netlist.

Some of this is historical. Traditional synthesis started as pure optimization of schematics and netlist. Then an RTL front-end was added to this logic optimization. When placement became important it was grafted onto the optimization but not the RTL stage. Oasys’s RealTime Designer, currently the only Chip Synthesis product out there, has been crafted from the ground up in the era of enormous timing and placement sensitive designs.

During DAC Oasys had parodies of the I’m a Mac, I’m a PC commercials with Synopsys and Oasys as the two characters. But in fact there is a deeper parallel: the PC was built incrementally with hardware from one manufacturer, a series of different very different operating systems (DOS, Windows etc) from another, bits and pieces from other hardware and software companies, support largely from nobody. By and large the Mac has been built holistically from the ground up including both the hardware, operating system and support (genius bars etc), all co-optimized to be a great solution that does everything cleanly.

The Entrepreneurial Engineer

EE Times has an interview by Sean Murphy with Paul van Besouw. It covers Paul’s background, leaving Cadence to found Oasys, and a good summary of where the company is today, including the agreements announced recently with Juniper Networks and with Xilinx.

However, I think the interview is interest to anyone running a small EDA company (or something similar) since it shows how Oasys bootstrapped themselves using sweat equity, then used the prototype to raise more money and ramped the company from there to the point that where it is today. Of course it is still a story in progress. Watch this space…

Cooley’s Deepchip highlights Oasys DAC videos

John Cooley’s website DeepChip is now highlighting the Oasys DAC videos. They were also referenced in his regular email blast to tens of thousands of users. From a position of obscurity not that long ago, Oasys has managed to get its message out to synthesis users pretty effectively. I’m sure anyone reading this has already seen the videos (they are on this site too) but just in case not they are on DeepChip here.