Oasys today announced support for SystemVerilog. In a related release Verific announced that Oasys had licensed the Verific SystemVerilog front-end.
SystemVerilog actually has an ancestry sharing a lot with Oasys. When Ambit was purchased by Cadence, Simon Davidmann, the VP of European sales for Ambit, along with some other Ambit people founded Co-Design Automation. The original version of SystemVerilog, then called Superlog, was developed there. Meanwhile, the founders of Oasys worked for several years at Cadence before leaving to create Oasys. In 2002, Co-Design Automation was acquired by Synopsys and Superlog was renamed SystemVerilog.
The Verific announcement is also interesting. EDA is littered with deals where one company OEMs a second, usually smaller, companies product. These deals almost never work since the customer has too little reason to buy from the re-selling company rather than going to the source of the product. The one type of OEM deal that does work is when part of a product, such as a front-end, is embedded in another product, such as a Chip Synthesis tool. Oasys already used Verific’s VHDL front-end and now they have licensed the SystemVerilog front-end.
September 20, 2010 — Oasys Design Systems announced today that it has added support for SystemVerilog to RealTime Designer™, its revolutionary new Chip Synthesis™ platform used in production flows at leading-edge semiconductor and systems companies worldwide.
“We are pleased and proud to have added System Verilog support within one year of delivering VHDL,” states Paul van Besouw, Oasys’ president and chief executive officer. “Design teams employing RealTime Designer are at the cutting edge of design and are increasingly using System Verilog.”
Support for SystemVerilog comes standard with RealTime Designer and is available immediately. In addition to SystemVerilog, RealTime Designer accepts Verilog and VHDL input, along with standard timing and physical libraries, SDC timing constraints and floorplans.
Chip Synthesis is a fundamental shift in how synthesis is applied to the design and implementation of integrated circuits (ICs). RealTime Designer is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs. It features a unique RTL code placement approach that eliminates unending design closure and iterations between synthesis and layout.
RealTime Designer follows a “Place First” methodology that takes RTL code, partitions it into blocks, places the RTL code in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement it until chip-level constraints are met.
About Oasys Design Systems
Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates. It has attracted the support of legendary EDA leaders and its RealTime Designer™ is in use at leading-edge semiconductor and systems companies worldwide. Follow Oasys on Twitter at: www.twitter.com/OasysDS. Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855- 8537. Email: email@example.com. For more information, visit: www.oasys-ds.com.
John Cooley’s DAC report seems to be coming out in installments this year, rather than an enormous report on everything. The section on Oasys is now out. There are a dozen reports by (mostly) anonymous engineers who saw the demo or, in one case, are in the middle of an evaluation of realTime Designer. A couple of the reports are quite extensive.
As one of the engineers says: “the company has vision, expertise, and a bright future.” Let’s hope so.