Several months ago, I was approached by Joe Costello, a member of the Oasys board, about joining. I had been an Oasys board observer for three years, representing an international angel investor, and watched its steady progress. It was apparent that Oasys is ready to take off. After five years of development time, RealTime Designer is proven with early customers that its dramatic benefits are really there, its performance is there as are its quality of results. I took one day to consider the offer and accepted because it is an exciting opportunity and a big market opportunity.
I like that the founders have worked together before and work well together. In fact, I am very impressed with the R&D team. It’s a smart group that works hard. It’s a well-oiled team with broad experience. All of them have worked on logic and physical synthesis in the past, some as part of the same team. They all work in the same office, a real plus when managing product development. The enhanced communication is a huge plus.
Also, Oasys has been able to grow due to the cash that is generated by customer adoption, which is not always easy for an early-stage EDA company. And, of course, Joe Costello. Joe is actively involved with the company and is available for strategy sessions, recruiting and visiting. He sees the potential.
What is really exciting, however, is the technology. It is really solving the next-generation design problems for large, complex, high-frequency chips, problems that existing tools don’t handle very well. The Oasys founders anticipated the next design challenge and set out to solve it.
We need to focus because, as a small team, we can’t do it all. We need to make our early customers successful. We also spend a good deal of time qualifying design environments that would benefit from RealTime Designer. We’re looking for prospects and customers who are willing to work with us to solve their tough design problems.
What design teams like about RealTime Designer is that, because of its amazing performance (10-60X existing synthesis tools and with equal or better QoR), they can go through many more iterations of their design to fine tune it. Where traditional synthesis can take days, we can do it in hours. We’re enabling design at 28nm and below, and design teams are impressed.