Over on Gabe on EDA, Paul’s prediction for 2011 that the focus will be on chips rather than blocks as designs migrate to 28nm and other tiny geometries:

2011 is going to be the year that a lot of 28nm designs are going to be undertaken and the design methodology defined. This is going to stretch the current block-based approach beyond breaking point.

So little of a chip’s performance or power can be predicted from simply looking at block-level netlists, that a full-chip approach will be required. This has already been a major problem at 45nm, resulting in endless iterations that do not converge. At 28nm, it becomes impossible to manually allocate the performance and power budgets among the blocks and then allocate each block to a designer. It will thus no longer be effective to “divide and conquer” to get around tool capacity limitations. Only when the blocks have been stitched back together again and physical design has been completed will it be clear what the performance and power of the chip will be. Since it takes a couple of weeks to go around this cycle, it is far too slow to get a design completed in a timely manner.

This is a huge challenge since big tradeoffs in performance and power must be done at the architectural level and captured in the RTL, but only after physical design has been done is it clear what the power and performance numbers actually are. Power, in particular, is a chip-level problem since usually it is battery consumption or heat dissipation that is the issue, rather than local temperature hot-spots. Trying to divide the design into blocks and then give each block a power budget in the 28nm environment is almost unworkable. Throw in multiple voltage domains, libraries with multiple power-performance points, libraries with high and low leakage cells and the problem becomes still more intractable, with complex interactions between performance, dynamic power and static power.

The solution is to handle the entire chip, or at least the largest blocks that comprise the physical hierarchy. Chip Synthesis does this, simultaneously optimizing for power and performance on a fully-placed design with a high correlation between the values reported and the values that will eventually be extracted after physical design is