Monthly Archives: March 2011

AE Stories #1

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Sometimes evaluations just go so smoothly it is hard to believe. Here’s the picture. The application engineer gets on a plane to go to a company in Europe. He lands on Sunday. Monday he’s raring to go but it turns out that it is a little known local holiday and nobody is working. Not a great start, one day behind already. Tuesday morning he arrives at the company and gets his hand on the design. It is 1.7 million instances and consists of about 30,000 files. It is the most complex design the potential customer has ever done.

The AE calls Paul that evening, “I’ve got a big problem.” Paul’s heart sinks.

The AE continues, “I’m done and my flight back isn’t for days.”

He had got the design through RealTime Designer about 1½ hours after walking through the door. The potential customer engineer’s assement: “This is unbelievable.” They are about to become a real customer (or a RealTime customer).

Gabe Moretti on RealTime power capabilities

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Gabe on EDA has a piece about the new power capabilities of Oasys RealTime Designer.

RealTime Designer follows a “Place First” methodology that takes RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement it until chip-level constraints are met.

EEtimes covers RealTime Designer’s Power Capabilities

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Anne-Françoise Pele of EEtimes has an article covering the recent announcement of power capabilities to RealTime Designer.

Oasys Design Systems Inc. has enhanced its Chip Synthesis platform, including chip-level power analysis and the ability to re-synthesize a design from the register transfer level (RTL) with new power constraints.