We have evaluated Oasys Realtime and, on a 1.5M-instance block, we saw a 48-minute runtime with production-worthy quality of result. This kind of runtime performance is necessary moving forward to tackle the coming design challenges.
We were looking at a list of the top US semiconductor companies the other day and we realized that those top 10 companies are choosing Oasys RealTime Designer for the complex, multi-million gate designs. In fact half of the (non-memory) semiconductor companies are already using RealTime Designer or are actively in the process of evaluating RealTime Designer for their most complex designs. And based on track record, once people evaluate RealTime Designer they become a customer.
Just today it became public that Texas Instruments (#4 in 2010) has become a customer, along with Netlogic Microsystems (obviously not in the top 10 but growing very fast).
So more and more of the top 10 semiconductor companies are “going big” and catching the Chip Synthesis wave. Come along to the Oasys booth 2031 at DAC. Or, better still, catch the Chip Synthesis wave yourself and have a demo of RealTime Designer synthesizing a whole chip including low power and scan-test. Sign up for a demo slot here.
DAC is coming up (June 6th-8th in San Diego if you’ve been hiding under a rock). The first year that Oasys went to DAC they had the revolution rockers video. Last year they had the PC/Mac parody videos. All the old videos are available to view on the video page here.
You won’t be surprised to know that this year at DAC Oasys has another video, this time about how major semiconductor companies are catching the big Chip Synthesis wave. They have water in an oasis right? So waves too? Well, just pretend. Anyway, I’m not going to give away too much, you’ll just have to come to see the video for yourself. Or, better still, catch the Chip Synthesis wave yourself and have a demo of RealTime Designer synthesizing a whole chip including low power and scan-test. Sign up for a demo slot here.
Oasys Design Systems is at booth 2031. Presumably we will put the video up on the website here soon after DAC for those of you that missed the wave to San Diego and are still paddling around.
Ed Sperling recently had another of his round-tables, this time on Power Budgeting. Paul was there. The transcript of the discussion is here.
A representative quote from Paul:
You don’t know until you go down to the placement how much power is really being consumed. You want to do the power optimization at as high a level as possible—at the architectural level. You want to design this at the chip level, not at the low level, but there’s also another problem. You need details. You need to know what’s being used. That will determine how you implement RTL.
If you would like a suite demo of Oasys RealTime Designer then request a time slot here.