Sandeep Bhatia’s article for Tech Design Forum is finally online.

The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.

For those of you that don’t know, Tech Design Forum has changed. It is no longer owned by Mentor but is now independent. The main journalists there are Paul Dempsey, Luke Collins and Chris Edwards. They are in the process of reorganizing the site as they take it over.

Paul’s predictions for 2012 are now up at EEtimes here and here.

First is about how power is the biggest problem and will continue to be:

The big issue in 2012 will continue to be power. The big challenge in designing an SoC is whether the entire chip can be lit up at once (answer “no”) and what to do about it. Multicore processors make this problem much worse since there is no point in putting an extra core on a chip unless it can also be turned on at the same time as all the other cores. Otherwise, why bother? Power has to be addressed at the architectural level, although there are certainly things that can be done downstream in the design flow to make incremental improvement. Power is a chip-level problem and needs to be addressed at the chip level.

Next is that noise will be a big issue:

A big issue for 2012 will be noise. Signal voltages are now down close to the noise voltages, which often don’t scale with the power supply at all. We are also getting closer to having to worry about counting atoms. After all, a 20nm gate is 200 hydrogen atoms across, or about 80 copper atoms, never mind how few atoms make up a gate oxide. Creating and analyzing physical design must be done at as high a level as possible, ideally at the chip level.

The other big question, that even we here at Oasys don’t yet know the answer to, is what will the Oasys DAC video be about:

At 65nm, the big issue facing designers was whether Joe Costello could be lured back into EDA if he was allowed to dress as a rock star. By 45nm, Apple had decided to move into IC design and make its own semiconductors, so the big question was whether Mac was superior to PC. At 32nm lithography issues dominated and the big question was whether it was possible to surf 193nm light waves to working silicon, going big and really small at the same time. For 2012 and for 28-22nm design, the big question remains to be defined but for sure will be on video in June. Editor note: hmmm, now what could that imply?