Gabe Moretti’s post-DAC newsletter hit the net last week including Paul’s retrospective on how DAC was for Oasys (well, it was certainly right here, right now). It is now online on Gabe’s website too.

Our first-ever floor demos showing why Chip Synthesis is a fundamental shift in how synthesis is applied to the design and implementation of ICs were well attended all three days and the feedback positive. The demo highlights the benefits of RealTime Designer, the first design tool for physical RTL synthesis of 100-million gate designs. It produces better results in a fraction of the time needed by traditional logic synthesis products through a unique RTL placement approach that eliminates unending design closure iterations between synthesis and layout.

Oasys RealTime Designer has once again made it onto Gary Smith’s list of what to see at DAC. As he says in his commentary:

Oasys continues to stick to their guns. Now that we have a SVP, and the resulting RTL Sign- Off point, more and more of the design will be handed off to Logic Synthesis with a Don’t Touch command. That means that Design Compiler’s superior optimization capabilities become less valuable than a synthesizer that can handle large designs. That doesn’t mean Design Compiler isn’t needed earlier in the design process, however today earlier often translates to the work being done by the IP vendor. This has given Oasys an opening that few suspected and they are taking advantage of it.

You can download the whole report and the list of companies here (pdf).

John Cooley has published his Cheesy Must See List for DAC 2012. Oasys is there again in the synthesis category.

Like last year (but with new $6 M in Series B funding) Oasys RealTime takes your RTL and floorplan to placed-gates “10X to 60X faster than Synopsys DC-Graphical can.”  Verilog, VHDL, System Verilog, MCMM synthesis, DFT, UPF/CPF low power design.  “Now we’ve done 28 nm tape-outs!”

He also speculates on what is under the hood in Xilinx’s Vivado:

Xilinx is chatting up its new Vivado Design Suite at this DAC, which I’ve heard is a combination of AutoESL (which they bought for $25 M back in early 2011) for SystemC/C/C++ synthesis, and Oasys RealTime (which they helped with $6 M financing) for Verilog/VHDL synthesis down to placed-FPGA-gates.