Oasys : Blog Page

Innovation of the year: go and vote

Gabe Moretti over at EDAcafe

SCDsource article on Chip Synthesis

Cooley's DAC report is finally out

Bryon Moyer comes to visit

The new release

Chip Design and the lyrics of the video

Binary Decision Diagrams

Aggregation of silicon

Sanjiv Kaul on why he's involved with Oasys

Jay Singh, Plato Networks

Harry the ASIC guy says "plausible"

Ten rules for corporate blog like this one

How did Oasys get started?

Rock star T-shirt signing

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Innovation of the year: go and vote

Feb 18th, 2010

EDN magazine has announced the finalists for its Innovation of the Year awards. Oasys RealTime Designer made the cut in the EDA: Front-End Analysis and Synthesis Tools category. The other four finalists are Jasper's ActiveDesign (formal verification), Synopsys IC Validator (I'm not quite sure even what this does: it is listed as in-design physical verification but that doesn't sound very front-end), Calypto's PowerProMG (power optimization) and OneSpin's RootCause (formal diagnosis). The winner is decided by votes cast (and you can only vote once). So go and vote for RealTimeDesigner.

Posted By paulm at 7:26 pm CST

EDA DesignLine

Feb 17th, 2010

There is a new piece up on EDA DesignLine (I think that’s how they write it, with a space after EDA but not after Design; when was it that companies started to write their names like variables in a C program?).

The article is in the usual house style of the websites that grew out of print where you are meant to maintain the fiction that, despite being written by the CEO of Oasys, the piece is just an survey of the industry and doesn’t mention the company by name.

It’s rather off-topic, but there is an interesting article by Michael Kinsely in The Atlantic Monthly about similar obsolete rules in journalism, where the journalist isn’t allowed to critique any statement by someone being interviewed. Instead, to be “objective,” the journalist has to find someone who has that opinion and present them as taking the contrary position, despite the fact that you may well never have heard of the person. Worse, the fact that the journalist works for a brand name newspaper or magazine may be the only reason to take the article more seriously than something by a blogger. But when things get technical, the bloggers tend to know their subjects much better than the supposedly more professional bloggers

Actually I overstated the case about product names. You are allowed one mention so both Oasys and RealTime Designer (I think I got the spaces right again there; when was it that product names...) slip into the final sentence, if you read that far.

And you should. I think that this is the best piece Oasys has written explaining how RealTime Designer works and highlighting just how dramatically different its results are compared with the usual synthesis suspects.

Share it with all your friends. Less fun that skateboarding dogs but more relevant if you are designing large chips and assembling the hundreds of jigsaw pieces of your chip into something that gets close to the picture on the box that marketing gave you.

Posted By paulm at 5:03 pm CST

Gabe Moretti over at EDAcafe

Jan 18th, 2010

Gabe Moretti has a piece in EDAcafe about Oasys. So get an EDAcoffee and go and read it.

It must have been a long time brewing (it's coffee all the way today) since it starts off with encountering Joe Costello and Nanette Collins at DAC (remember that back when San Francisco wasn't cold and wet). But I think his key quote is that he considers that Oasys is "one of the dwindling number of EDA startups that can be successful." Coming from Gabe, who is not noted for being over-optimistic that is high praise indeed.

Gabe also makes the point about how the founders of Oasys had to leave Cadence in order to develop RealTime Designer, rather than being allowed to do it within Cadence. To be fair, Cadence has tried to incubate products internally with more of a startup culture. The Catena router was developed in a skunk works in Los Gatos; the C-to-Silicon was another attempt to get a startup mentality into an internal group. But there is a more fundamental problem: for any given product, one that is not incremental off the existing technology but one that is disruptive, there may be half-a-dozen groups that might be the one to develop breakthrough technology and produce the market leading technology. If one group is internal that is still only a 1 in 6 chance that the internal one will be the winner, and a 5 in 6 chance that an acquisition is a more likely method to get the best technology. Another issue is how to compensate employees in an equivalent manner. If Oasys is wildly successful then the founders will make a lot of money. If they had stayed at Cadence and managed to develop the same successful product then not so much. So why would they stay?

Anyway, they left. Gabe wonders why they did it given that EDA is a market in either secular decline or anemic growth depending on your point of view. But nobody is predicting explosive growth for EDA as a whole. But synthesis is a $350M market and a startup doesn't need to win much of that to be a large startup. In addition, Oasys is biting off a big enough piece of the pie that the interfaces are simple and customers who adopt it will not spend multiples of what they gave Oasys in developing a method to integrate it clumsily into their flows.

Gabe worries about what will happen when Oasys outgrows its market and has built a solid differentiated business. My answer would be that I can't think of a nicer problem to have but that it is hard to plan for when you don't know how the EDA landscape will look in a few years. My own belief is that if Oasys is successful at building a large fast-growing business and are several years ahead of the traditional EDA company's synthesis products then one of the big guys will acquire them, whether that is what they plan or not. Every company is for sale every day, it's just a matter of price.

Gabe doesn't like the name Chip Synthesis since the chip is the final product, not what comes out of synthesis. He thinks "Design Synthesis" would be better. But I think that sounds rather too like the name of a synthesis product from a well-known EDA company with a purple logo. But then I don't like the RealTime in the product name since it sounds too like something in the RTOS embedded space. Oh well, people are never happy with product names.

So, today's trivia question: what was the name of Berkeley's first logic optimization tool? Espresso. I told you it was coffee all the way.

Posted By paulm at 7:58 pm CST

Welcome 2010

Dec 26th, 2009

Oasys had their holiday party last week. The end of the year is a time for both looking back and looking forward. Certainly 2009 has been a wonderful year for Oasys. The capabilities of RealTime Designer have become well-known since DAC. There has been good coverage in what remains of the EDA press and blogs, almost all of it starting off with the attitude that it's too good to be true before coming around to the view that it might, after all, really be a genuine next generation product and not just incrementally better than the traditional synthesis products out there.

But looking forward 2010 is clearly even more significant for Oasys. This is the year in which Oasys will either take off or flame out. Everyone likes the story of RealTime Designer; what's not to like. But in 2010 designers need to be taping out real production chips and the business people need to be making real volume purchases. Startups have a tempo of their own and success cannot be too long coming for all sorts of reasons: money, morale, marketing.

So happy new year to everyone and watch this space in 2010 as the story unfolds.

Posted By paulm at 3:30 pm CST

SCDsource article on Chip Synthesis

Dec 15th, 2009

There is a new article on Chip Synthesis up on SCDsource. Due to their editorial policies, which mean you are not allowed to plaster the article with product and company names, you have to read between the lines to deduce that Chip Synthesis really means Oasys RealTime Designer. But, hey, if you are smart enough to design a chip you are smart enough to work out that Paul (vb, not me) is probably not talking about a new release of DC.

Posted By paulm at 12:00 pm CST

Cooley's DAC report is finally out

Dec 11th, 2009

John Cooley's DAC report is out (remember DAC, it was that conference back in June) and Oasys gets the first section all to itself. As Cooley says, "Aart de Geus would have a heart attack if he knew the names of his Tier 1 customers anonymously commenting here about Oasys." There are many people listing Oasys RealTime Designer as one of the few (or in some cases the only) interesting thing that they saw at DAC. So go over there and read the detailed comments.

Posted By paulm at 11:59 am CST

Bryon Moyer comes to visit

Dec 1st, 2009

Bryon Moyer, over at IC Design and Verification Journal, has a nice description of spending an afternoon at Oasys getting a demo of RealTime Designer. Like many people, he starts of skeptical that Oasys really is doing anything qualitatively different from other synthesis companies, skeptical that Chip Synthesis is anything other than a marketing gimmick to try and position Oasys as "new, washes whiter." But by the end he is much more open to the idea that this really is something different.

He finishes up with the key business question:

“If this is so great, why isn’t everyone using it?” Which elicited the obvious answer: people are slow to change; it’s a major design flow upset; it doesn’t happen overnight. Meaning that either they should see some good traction at some point or someone will call them on smoke and mirrors.

This is clearly the challenge for Oasys in 2010. The technology looks great, but can real companies really leverage it in real designs? Are the initial pipe-cleaner designs successful enough that proliferation in large semiconductor companies takes place? From the users I've talked to I think the answer will be yes, but of course Mr Market will decide.

Posted By paulm at 2:31 pm CST

The new release

Nov 28th, 2009

Oasys announced a new version 9.3 of RealTime Designer with two main new features. The first is support for VHDL.

VHDL is, of course, one of the two main hardware description languages dating back to the 1980s. The history of Verilog and VHDL is quite interesting. Verilog was originally created by Gateway Design Automation. Gateway was subsequently acquired by Cadence for what seemed like a very high valuation at the time, although of course it has probably been one of the most successful acquisitions Cadence did when you think of the sales of Verilog that they have made over the intervening years. VHDL, which is actually one of those nested acronyms since it stood for VHSIC Hardware Description Language, with VHSIC further parsed down into Very High Speed Integrated Circuit. The VHSIC program was run by the US DoD and VHDL looked for a time that it might become the dominant standard, since Verilog was a proprietary language owned by Cadence.

But Cadence opened Verilog up and let other people participate in driving the language standard. As Gordon Bell once said, the only justification for VHDL was to force Cadence to put Verilog into the public domain. But having two languages has been a major cost to the EDA industry for very little gain. VHDL was a very powerful language but in many ways was less practical than Verilog. For instance, you could define your own values for any signal. But that meant that gates from one library wouldn't necessarily interact properly with gates from another library (sounds like some of the problems with TLM models in SystemC that are finally being resolved). So that required a new standard, VITAL, so that gate-level signals were standardized. The richness of VHDL abstractions meant that it was and is used for some of the most complex communication chips. Model Technology (now part of Mentor) had probably the best VHDL simulator that they sold cheaply, and that helped to make VHDL more standard in the FPGA market than Verilog. Despite the fact that a Verilog simulator is easier to write than a VHDL simulator, it sold for a higher price for years. This has led to an odd phenomenon where some of the most advanced chips are done in VHDL, and many of the simpler ones.

Anyway, the dual language environment (and, of course, SystemVerilog has arrived to make a third) continues to exist, and now VHDL users can take advantage of Oasys's Chip Synthesis technology with its huge capacity and very accurate timing prediction. Of course Oasys is focused on the biggest designs (not that you can't use it for small ones) so it now addresses these large VHDL designs.

The second feature is multi-mode sythesis. Often designs have more than one mode of operation, such as a test mode for testing the chip and a normal operational mode. Years ago people didn't worry too much about the test mode and would assume it would "just work." But in modern processes and the modern speeds for testing that approach isn't very effective. The synthesis tool needs to take both sets of constraints into account and ensure that timing constraints are met both in the operational mode (in the system) and the test mode (on the tester during manufacture).

Posted By paulm at 3:50 pm CST

Chip Design and the lyrics of the video

Nov 23rd, 2009

Posted By paulm at 4:34 pm CST

Binary Decision Diagrams

Nov 10th, 2009

Last week was the EDAC Kauffman Award dinner. One minor advantage of being a blogger is that I got invited along as press. Will blog for food. This year’s winner was Professor Randal Bryant, usually just known as Randy Bryant.

I knew of Randy as the inventor of switch level simulation with a tool called MOSSIM. Up until that point, all simulation of semiconductor had been done using Spice type algorithms, worrying about the transfer functions of the transistors. But with the coming of Mead and Conway, computer scientists were starting to want a much simpler model of the world so that they could apply programming techniques to design. Treat transistors as switches that were either on or off and with a unit delay (all transistors turned on and off at the same speed). MOSSIM was the first of these so-called switch level simulators developed in about 1980. Later, the switch model would be enhanced to add timing. Funny now to realize that in the early 1980s IC design was largely done without timing, using Spice for paths that looked like they might be important.

Randy Bryant was also the inventor of BDDs, binary decision diagrams. BDDs are a very efficient representation of combinational logic and are one of the key technologies underlying logic optimization and hence underlying both synthesis and formal verification. The advantage of BDDs is that despite being a fairly compressed representation of the circuit, many logic operations can be done efficiently directly on the BDD, without needing to expand the representation into something less space efficient and then recompress it again afterwards.

Randy first published his ideas in 1986. An amazing fact that came to light at the Kauffman award dinner was that his paper just kept getting more and more citations. Usually a paper generates a flurry of interest soon after publication and then it dies down. But 15 years after publication for most of the early part of this decade, Randy’s paper wasn’t just the most cited paper in EDA, it was the most cited paper in the whole of computer science.

Every synthesis and formal verification tool relies heavily on BDD representation internally. Of course, Oasys Realtime Designer is no different, although since it doesn’t attempt to operate on the entire design simultaneously at netlist level it is perhaps less critical from a memory point of view.

The Kauffman Award is awarded based on the impact that individuals have had on EDA. The ideas in MOSSIM, while very important in the early 1980s have dwindled in importance since simulation has moved up to higher levels. But given that every synthesis and formal verification tool including Oasys Realtime Deisgner relies heavily on BDDs over 20 years after their conception I think that the “impact” is unarguable.

Posted By paulm at 1:14 pm CST

Aggregation of silicon

Nov 8th, 2009

Last week at ICCAD, Jim Hogan and I led an discussion on the megatrends facing electronics and the implications going forward for EDA. Basically we took a leaf out of Scoop Nisker's book, who when he finished reading the news would sign off with "if you don't like the news go out and make some of your own." So we tried to.

The basic premise that we put forward is that end markets are fragmenting, meaning that designs need to be done in smaller volumes, but meanwhile semiconductor technology is pushing design costs so high that few markets are large enough, hundreds of millions of units, to support designing a 45nm chip with its $50M price tag.

As a consequence of this mismatch, designs need to be aggregated in some way so that many systems are constructed out of the same chip(s) so that the chip volumes are high enough to be economical. So FPGAs are likely to become more important going forward, and in fact this is seen in the way that the high end of FPGAs is growing fast.

This has the potential to be good for Oasys since one of the limitations on using FPGAs today are that the synthesis technology is slow and lacks a lot in terms of predicting eventual performance. These FPGAs are huge and complex (including embedded software) and so the old “blow and go” method of simply implementing the design is not adequate for verification going forward.

The big challenge for EDA in general, and this will affect Oasys too, is that the channel required to sell software largely to a couple of dozen large semiconductor companies is not the same as that required to address a much larger market of smaller players. What the correct price points are is also unclear. But electronic design is going in this direction and EDA will have to follow.

Ultimately this is moving towards what I call software signoff, the inversion of the way about thinking about electronic systems. Instead of thinking of a complex SoC with some embedded software, a system is actually a big software system, parts of which need to be accelerated by some type of semiconductor implementation to make them economic (fast enough, low enough power). We don't yet have the tools today to take complex software and automatically build some parts in gates, assemble IP, assign the software to processors and so on. But that is the direction we need to move in and the type of very fast, very high capacity, very accurate synthesis that Oasys is pioneering will be an important piece of this puzzle.

The mismatch between fragmented end-markets and high costs of design is potentially disruptive and thus an opportunity to change the way that design is done. I return to Yoshihito Kondo of Sony's call to arms: "We don't want our engineers writing Verilog, we want them inventing concepts and transferring them into silicon and software using automated processes." Oasys has important technology to enable this transition.

Posted By paulm at 3:51 pm CST

Renesas

Oct 3rd, 2009

Last weekend I talked to Yoshio Inoue of Renesas. It was a convenient 3pm on a Friday afternoon for me but it was 7am on Saturday morning in Japan, so definitely going beyond the call of duty.

Renesas, in particular Inoue-san and his team, was one of the earliest companies to use Oasys RealTime Designer. They have been working with Oasys for about two and a half years. He considers that it is the most advanced synthesis technology and has the potential to start to change the usage model and is the missing link to drive chip implementation up to a higher level. Their experience is that it is 100 times as fast as other synthesis tools. For example, on one 22 million gate design, also including 500 memories, the entire chip is synthesized from top level RTL to placed gates in about an hour. He says it produces better results than other synthesis tools in a fraction of the time.

Of course in the early days there were the usual teething problems of any immature tool such as consistency issues between placed gates from RealTime Designer and the detailed timing after final place and route.

Inoue-san plans to transition to RealTime Designer for final synthesis but right now doesn’t have the budget to get all the tools he needs. It is no secret, as he put it, that “currently Japanese business is not very good, also Renesas too.”

Today, it is their most experienced designers who are using RealTime Designer. They have used it on designs that are simply too difficult to do bottom up with traditional synthesis tools. The great thing about doing design top down is that you can see the global nets, which are the ones that typically cause problems with closing timing in a bottom-up approach. This is very difficult with Design Compiler (mainly because the speed is so slow even though eventually results may be acceptable).

Historically Renesas has been very strong on floorplan and, in particular, getting to a good floorplan early. It is too late to wait until physical design begins to create a floorplan, but front-end designers are simply not very good at this. There is a discrepancy between the mindsets of front-end and back-end designers which makes this a challenge. Front-end designers simply do not understand physical constraints like I/O and RAM placement and so sometimes produce floorplans that are garbage but without any tools to make this clear. RealTime Designer, which can synthesize the whole chip into a given floorplan helps make this problem less severe by exposing poor floorplans early so that they can be altered when it is still early and easy to make such changes.

Looking to the future, Inoue-san sees RealTime Designer as a key piece of the puzzle of driving chip design up to a higher level, the other pieces being high-level synthesis (HLS) and floorplanning that works at that level.

Inoue-san wants to be able to regard RTL simply as an “intermediate code” that is generated from higher-level tools. They are also a lead customer for Cadence’s CtoSilicon HLS product. He wants move away from treating RTL as something a person writes, to something that is only written by other tools. But this approach only work if there is a tool that can consume the entire block or the entire chip, and reduce it to place and timed gates fast enough that the designers can get the feedback they need to make design tradeoffs. Oasys RealTime Designer is this missing link, able to take the entire chip and turn it into placed gates in very short timeframes.

Oasys is then the tool that consumes that RTL. However there are weaknesses in the approach today since c2silicon is not good enough for control which means that some RTL still has to be created by hand. It is like programming in the 70s where high-level languages could be used much of the time, but sometimes it was necessary to write critical pieces in assembly code.

Going forward, Inoue-san reckons that either high-level synthesis needs to get good enough to handle the whole design, or Oasys needs to move up and support high-level synthesis directly in the future, or perhaps some API-based combination of the two synthesis levels. That is what is needed to be able to completely hide RTL from a design point of view. RealTime Designer is the only tool that can form the foundation for that methodology transition which will drive up the level of abstraction used by designers to C/SystemC and potentially create a disruptive step-function in designer productivity.

Posted By paulm at 12:11 pm CDT

Genomes

Sep 10th, 2009

What do genomes have to do with chip synthesis? When Oasys started, they needed a name for the RTL partitions that are the heart of the chip synthesis approach. They decided to call them genomes since in a way they embody the DNA of the design. Of course to start with, this was just an internal name as they developed the code. When they started to present the product to potential customers, they continued to use the name genome since it is catchy. However, that turned out to be a mistake. Everyone focused on the name, since it is catchy, and wanted to know how it related to real genomes, and precisely what was in a genome and so on, and got completely distracted from the results of the chip synthesis process.

EDA tends to be like that. Designers don’t just want to know how good the results are, they want to understand the internals of the tool to convince themselves that the tool works since actually doing an evaluation is too expensive. It’s as if when an EDA engineer goes to buy a car, instead of taking a test-drive, they take off the cylinder head and check the camshaft angles.

Anyway, the name genome is no longer used and they are just referred to as RTL partitions, which is less catchy but sufficiently descriptive not to be distracting. So what are these RTL partitions aka genomes?

Once the RTL has been read into Oasys RealTime Designer, it is divided up based on connectivity into smaller blocks that will eventually be implemented as a bunch of gates. The partitions are small enough that they won’t contain any long wires, which would lead to high variability in timing, but large enough to have implementations with potentially different space-time tradeoffs. Each partition is largely independent of the others. Of course the timing of all the other partitions is required to be able to time the whole chip, but the detailed internals of every partition are not required at the same time. Since it is no longer necessary to look at the whole chip at the gate-level at the same time, then the memory requirements are hugely reduced. The old approach to synthesis does all the optimization at the gate-level and requires a huge amount of data for every gate to be around in memory simultaneously, which is why it has such a low ceiling on the size of block that can be efficiently synthesized.

The RTL partition approach is the main reason that Oasys RealTime Designer can be so fast and so effective. By operating at a higher level, it intelligently synthesizes and times the design one partition at a time. Then, until timing is met, it re-synthesizes, re-places (and updates the global routes) and perhaps re-partitions parts of the design until the constraints are met.

Posted By paulm at 9:22 pm CDT

Sanjiv Kaul on why he's involved with Oasys

Sep 9th, 2009

By Sanjiv Kaul, Executive Chairmain, Oasys Design Systems, Inc.

Several people used to ask me questions about why I am involved with Oasys both as an investor and an active Executive Chairman. Why did you invest in Oasys? Isn’t EDA in trouble? Aren’t EDA startups having a hard time? Even if your technology is good, isn’t it very hard for a startup to build a business in EDA?

All good questions. Investing in EDA can be hazardous to your wallet! The Oasys story is still being written but I thought I would share my insights. Monday morning quarterbacks are always right, but it is the analysts who can read the game while it is being played that are worth listening to. So let me try and put my mouth where my money is.

There is a reason why so few EDA startups are successful. Too many EDA startups are launched with a quick acquisition in mind. Often they are better implementations of key features in an existing design platform. Such start ups typically have a hard time making it. Not only is integrating that product into existing flows hard but typically the large companies focus resources to close the gap especially if the startup is getting traction. There has to be a sustainable advantage that is meaningful to customers for a business to be successful

When Paul, Harm and Johnson first pitched the Oasys idea to me I was immediately attracted to it. There were several reasons:

1. Oasys was trying to address a real customer pain. Current synthesis technology was getting increasingly inadequate for design teams doing large chips. The run times were too long, managing constraints for 100s of blocks too cumbersome, and the results coming out of synthesis were not very meaningful given the big impact of floorplans and physical implementation.. As a result the timing closure problem was increasingly a back end issue and synthesis was becoming commodity. Most high end teams have all the different synthesis solutions available to them and use the output of whichever one delivers the best results after P&R.

2. The Oasys solution was going to be a complete platform. That meant it would be possible to build a sustainable advantage over the competition because the product depended on standards to interface into design flows.

3. What the Oasys founders wanted to do was pretty audacious. But that is what it takes to be successful as a startup. In EDA if you don’t have a 10X advantage at least, it is hard to break through the all you can eat, preferred vendor deals that the major EDA vendors like to do with their major customers. Customers will not switch in a big way to new technology from a startup unless they see a sustainable lead. If Oasys accomplished what it wanted to do, then Oasys would have a 4-5 year lead over the incumbents. Synopsys was quickly able to close the technical gap with Ambit and so it disappeared from the market. With RC Compiler, it has taken Synopsys longer and that is why RC has decent market share.

4. The Oasys solution is so different from existing synthesis solutions that it is a new product category: Chip Synthesis.

5. The founders felt they could develop the product with a limited investment. That was key, given that EDA had fallen out of favor with Sand Hill Road.

6. There was a large addressable market. If you don’t see a path to a $100M business for a start up then you should not do it in my opinion. It is as hard to build a $10M company as it is to build a $100M company. But your chances of success are much better with the $100M play.

After I joined the initial angel investors, Paul and his team went away and worked on the technology. They came back after two and a half years and said that they thought they had done it! Oasys asked me to join the Board to help drive the company to the next level. I was excited about the technology but also a little skeptical. How would the product hold up on different kinds of designs? Was the product full featured? Could customers deploy this product? Too many EDA products have too small a sweet spot. They do well on the initial carefully selected benchmarks but falter on different design styles.

So we spent the next two years validating the Oasys solution on different design types and converging with customers on needed functionality. The key was to deliver the best starting point for physical implementation. That meant producing placed netlists that delivered targeted QoR after P&R. That meant going smoothly through all the popular P&R systems . That meant helping design teams to converge to their floorplan as early in the design process as possible.

It was only after carefully proving out the product that we announced the company and the product. Oasys has a long road ahead. But as our mothers used to say, “A task well begun, is half done”!

Posted By paulm at 3:43 am CDT

Jay Singh, Plato Networks

Aug 28th, 2009

Last week I met Jay Singh of Plato Networks. He was one of the earliest users of Oasys RealTime Designer and I wanted to find out what his experience was. Jay got involved with Oasys early on, before the tool was mature, and has given a lot of feedback over the last year and a half.

A bit of background on Plato. They are building 10 gigabit PHY solutions for the next generation of data centers. Big complex chips with enormous amounts of interconnect.

Jay thinks that it’s great that RealTime Designer is so fast but that is not the most valuable aspect of it for him. The biggest strength is the consistency of the results from synthesis with what comes out after place and route. But it is fast. On difficult blocks he found that it was 20x to 60x the speed of traditional synthesis tools.

If he provides a floorplan, then he reckons the results are 100% predictable. What RealTime Designer says is what you will get. Furthermore, you’ll get it faster since the netlist seems to be very friendly to the place and route tools and designs seem to go through physical flow much more quickly and smoothly. Speed improvements of up to 3X  have been observed in the existing backend flow, using same set  of scripts, simply by swapping traditional tool netlist with the RealTime Designer generated one.  You simply don’t get that consistency with other synthesis tools. With them, after place and route the results may be better or they may be worse than predicted. The prediction simply isn’t very good. To cap it off, in some cases the blocks are 20% smaller than with traditional synthesis.

One interesting thing I didn’t know is that RealTime Designer sometimes creates more instances than traditional synthesis, which typically works hard to reduce instance count. For example Jay saw 2.5X more instances in a connectivity-intensive design and despite that the backend physical implementation had more than 2X speed improvement over traditional synthesis.

Why is this? Oasys knows timing and placement from the very beginning. Traditional synthesis tools simply try and minimize the instance count. This used to be a sensible thing to do but now that interconnect is as a big a problem as cell area that doesn’t seem to be true any more. To take a simple example: if a signal is used in two places on a chip, and its inverse is also needed in both places, traditional synthesis tends to create one inverter and then run the inverted signal to both places that it is needed. If those two points are close together then this is a good decision. If they are far apart, it makes more sense to put a small inverter at both points, which pushes up the instance count but removes a long wire and reduces congestion. Decisions like this about how to structure the netlist can only be taken when the RTL, the placement and the timing are all available at once, which is just the approach taken by RealTime Designer.

His view of adoption of RealTime Designer is that the scripts are very simple. It is easy to use and the commands are very consistent with other synthesis vendors so there is a shallow learning curve. In fact, because RealTime Designer just takes the entire design and synthesizes it, there are only a few commands that get used much. Cross probing between schematic and RTL source works really well.

It runs perfectly in batch mode and Jay likes to set it up to run a whole matrix of different performance tradeoffs overnight since it is so fast. In effect, instead of using intellect to work out how to tweak the performance, just burn up lots of computer time (cheap) and do 20 runs. It has the features of other synthesis tools but Oasys have made it simpler.

Posted By paulm at 12:31 pm CDT

Harry the ASIC guy says "plausible"

Aug 17th, 2009

Harry the ASIC guy already blogged once about Oasys, pretty much with the skeptical view that Oasys’s results were too good to be true, it’s Ambit or get2chip all over again, and who cares about synthesis anyway.

But he came back and took a real look, getting the suite demo during DAC. His second blog on Oasys starts off with the same Groundhog Day, story repeating itself point of view. But Paul did more than give him a demo, he explained at least a little of the secret sauce inside Oasys:

According to Paul van Besouw, Oasys decided to take an approach they call “place first”. That is, rather than spend a lot of cycles in logic optimization before even getting to placement, they do an initial placement of the design as soon as possible so they are working with real interconnect delays from the start. Because of this approach, RealTime Designer can get to meaningful optimizations almost immediately in the first stage of optimization.

A second key strategy according to van Besouw is the RTL partitioning which chops the design up into RTL blocks that are floorplaned and placed on the chip. The partitions are fluid, sometimes splitting apart, sometimes merging with other partitions during the optimization process as the design demands. The RTL can be revisited and changed for a new structure during the optimization as well. Since the RTL partitions are higher-level than gates, the number of design objects in much fewer, leading to faster runtime with lower memory foot print according to van Besouw. Exactly how Oasys does the RTL partitioning and optimizations is the “secret sauce”, so don’t expect to hear a lot of detail

Interestingly, I’d written a blog entry before DAC giving an overview of some of the technology under the hood, since I thought that people are very skeptical of “trust us, we’re clever” as an explanation of how Oasys can do something that Synopsys et al cannot. And, during demos at DAC, people wanted to have at least an idea of how the tool worked so that they could convince themselves that it might be as good as the writing on the box claimed. But we decided it gave away too much too early and so it hasn't yet run.

Harry the ASIC guy ends up doing a Mythbusters on Oasys, to decide whether their claim is “confirmed” or “busted.” Having started off very skeptical, once he understood some of the way the tool worked, he at least got himself to “plausible.” Of course, like anyone, he wants to see the tool run on a variety of designs in a non-demo situation. All tools look good in demos since it is a very controlled environment. Plus there are various things that Oasys RealTime Designer does not yet address, most notably support for CPF and UPF.

There are some interesting comments on Harry’s blog entry too. Cadence objects that RTL compiler isn’t at all like Design Compiler, Rubix thinks that Oasys needs a clock optimization tool like the one from, say, maybe, Rubix. And everyone points out that marketing claims aren’t worth the paper they’re not printed on any more, it all comes down to benchmarks.

Actually, I don’t think even benchmarks are that interesting. In the end, the most convincing thing of all will be when some of Oasys’s customers go public on the designs that they have successfully taped out. As Harry says, this is the gold standard of EDA: are the dogs eating the dog food?

Posted By paulm at 6:42 pm CDT

Ten rules for corporate blog like this one

Aug 10th, 2009

I only started blogging on EDAgraffiti at the start of the year and over here just a couple of weeks ago. The two blogs are very different, one being essentially my opinion on whatever I feel like giving my opinion on, and the other being a corporate blog. I came across and interesting list of ten rules about corporate blogging that is worth thinking about. I won’t cover everything it says, you can read the whole thing.

But here are the ten rules with a couple of comments:

A blog does not magically generate traffic.
A good corporate blog requires long-term commitment.
Teaser feeds are a wasted opportunity.
You are not “engaging” anyone.
Press releases shouldn’t appear on a blog.
You sound like a faceless corporation.
You need to show the warts and all.
Marketeers often make bad bloggers.
You expect too much from your readers.
Your competitors will read your blog; get over it.

Items 1 & 2 are really an admission that you have to earn the right to be listened to and that, now matter how good the content, building a readership takes time.

Items 3 & 4 are not yet relevant to the Oasys blog since we’ve not (or rather not yet, I hope) set up either RSS feeds or comments. So this blog is still very much in broadcast mode rather than anything approaching a conversation.

Items 5, 6 and 7 are about making sure that this blog has a more human face. People like to talk to people not corporations. Scoble’s blog at Microsoft was wonderful at this, putting a human face on Microsoft at least partially by being tough on Microsoft in areas where Microsoft was not perfect (aka sucked).

Item 8: well, I was an engineer before I was a marketeer. Also, my plan with this blog is to get other people (customers, engineers etc) to write some of the content. It can’t just be a marketing channel or it fails to earn the right to be listened to.

Item 9: be punchy. Both in the sense of being brief and in the sense of being edgy.

Item 10: Hi there Synopsoids.

Posted By paulm at 12:01 pm CDT

How did Oasys get started?

Aug 6th, 2009

There were three founders of Oasys, Paul van Besouw, Johnson Limqueco and Harm Arts. When we all worked together at Ambit, Paul was the lead for the “front end”, the RTL synthesis part of the product, and Johnson and Harm were the main engineers working on the “back end,” the gate-level optimization. Everyone knew that wireload models were at the end of their useful life and so like every other synthesis team Ambit also had a physical synthesis project, PKS.

Building an old-style synthesis product, and bolting on physical optimization convinced the three of them that it was the wrong approach. The first thing a modern place and route tool does is usually to remove all the buffering and downsize all the gates, so it didn’t make a lot of sense to spend a lot of time in synthesis carefully creating them. But at least down to about 0.1um that approached worked well enough to get timing closure. However, in a current generation process this fails since the netlist that comes out of synthesis is not a good starting point to get to one that actually closes timing since it typically requires more aggressive changes to the netlist than the place and route tool is capable of. So sometimes the netlist that comes out of synthesis closes easily, perhaps wasting area; sometimes it is impossible to close. The reality is that the “timing” of the netlist that comes out of synthesis bears almost no resemblance to the timing of that netlist once it has been through place and route. This is such a large problem that ASIC companies are apparently asking customers to have 50% timing margin to give themselves some chance of closing timing.

In an old-style synthesis tool, the RTL synthesis is done naïvely. The RTL is parsed and transformed into a control/dataflow graph (CDFG). This graph is then walked and an initial implementation into gates and registers is created without any regard to timing or other constraints. In fact the timing engine isn’t even turned on at that point. A level of optimization then takes place analogous to Karnaugh maps. After that the gate-level optimization really goes to work and grinds away. And grinds away. And grinds away until hopefully the timing constraints are met or heuristics decide that it is time to give up. It is only at this stage that physical information is taken into account, but due to capacity limitations, the synthesis hierarchy doesn’t match the physical design hierarchy and the physical information is basically bogus. It is here that Johnson and Harm’s complaints “give us a better netlist Paul” was one of the motivations to create Oasys.

Why not put all the effort into generating a really good placed netlist from the RTL? So good, in fact, that a traditional optimization back end would not be required. It wasn’t clear whether it would be possible to build a front end that good, but it seemed worth a try. So the three of them designed the basic architecture of a Chip Synthesis product and started to code.

That was 5 years ago. If you design a tool in a completely new space, then early customers might be interested in it when it is still half-baked. It may still deliver value that they cannot get in any other way. If you design a tool in an existing space, then early adopters really are not interested until it starts to get better results than the existing solutions, which is a much higher bar. A lot of code and a lot of testing has to take place before any tool is better than Design Compiler, the main incumbent. Eventually Oasys got there and the performance and capacity were compelling to some early adopters. They were on their way.

Posted By paulm at 10:02 am CDT

Rock star T-shirt signing

Jul 29th, 2009

The rockstar T-shirt signing took place this afternoon. As planned, it drew a large number of people to have their T-shirt's signed by Joe, Sanjiv and Paul. Here's Joe signing my T-shirt.

Posted By paulm at 7:22 pm CDT

DAC so far

Jul 29th, 2009

This blog comes to you live from the show floor at DAC. The show is going well for Oasys. It was busy yesterday (never underestimate the value of something being free, like Monday at DAC) but it is much quieter today. However, the key measure f success is not so much how crowded the corridors are but whether the demo suite is full with potential customers. By that measure the show is a success.

The rock video is also a success, drawing a crowd when it runs on the half-hours. It’s only meant to get the Oasys name out there, so it’s doing its job. Let’s see if Joe and the guys in full costume tomorrow will draw a big crowd.

We’ve turned the sound down a bit out of respect for our neighbors on the floor. Having been there myself, I can tell you that it is no fun to be on the booth staff and have to listen to a pre-recorded video for the fortieth time. Of course the Oasys booth staff have to do that but at least they are eating their own dogfood, as it were.

Gary Smith talked about Oasys in his overview of the EDA industry on Monday morning. That was the good news. The bad news was that he listed Oasys as a supplier of ESL synthesis.

Posted By paulm at 12:20 pm CDT

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