One of the challenges with design flows involving high-level synthesis from C, C++ or SystemC is that eventually the exact performance of the design needs to be determined. The built-in metrics in HLS tools are fairly good at determining which of two implementation choices has the highest performance or consumes the least power and can thus guide the exploration of the design space.

However, sooner or later the actual performance or power numbers are required. If a design is to process 30 frames of high-definition video per second then 29 just doesn’t do it. And probably 50 frames per second would be wasting a lot of power and silicon area.

Traditional synthesis followed by placement is a cumbersome way of getting at this data. Chip Synthesis using Oasys RealTime Designer is much smoother, getting to a fully-placed design with accurate performance numbers in a short time. HLS can produce a lot of RTL, tens of thousands of lines, very quickly. Luckily RealTime Designer can easily process this fast to get the data that the system level designer needs to finalize a choice of implementation.

Paul van Besouw from Oasys and Devadas Varma of AutoESL have jointly written an article for Embedded Computing Design on just this topic.