Shankar Vellanthurai, Director of Field Applications Engineering, Oasys Design Systems
Recently Oasys was working with engineers at a networking company that produces SoCs for their routers. This SoC design team hands off a Verilog netlist to an ASIC services company for chip finishing once their RTL has been verified and synthesized. The SoC team had to wait for six to eight weeks before they got any feedback from their ASIC services company on the feasibility of the physical design of their RTL, which included things like area, power, routability, and timing closure.
Their existing design flow was to use physically-aware RTL synthesis with 10% timing margins. The SoC was partitioned into several sub-blocks and these sub-blocks were synthesized separately and then assembled at the top level along with some glue logic. This flow required running approximately ten block level and one top-level synthesis runs to assemble the chip. The engineers created timing budgets for the block level design constraints which made the top level timing closure difficult and time consuming because of incorrect budgeting for some of the blocks. To add to their schedule woes, the engineers were shown routing congestion issues after placement and routing that required further modifications to their RTL code.
This inability to see the routing congestion issues during the synthesis phase added additional and unplanned time to their design schedule. Each time they created a new netlist they had to wait for their ASIC services company to provide feedback on the routing congestion and timing closure issues, which added one to two months to their design cycle each time they modified their RTL.
The SoC team was looking for a SoC design tool that could synthesize the entire chip in a top-down manner without having to partition the design into sub-blocks with unrealistic timing constraints. The engineers also wanted to see a tool that was physically-aware similar to their ASIC services company’s placement and routing tool suite which could provide early visibility into routing congestion and top-level timing.
The SoC team had seen the Oasys RealTime Explorer demo at DAC 2012 and was hopeful that this new tool could solve their schedule problem. The SoC team contacted Oasys and requested to use RealTime Explorer on the RTL of their SoC designs. The Oasys license and software were installed and up and running in less than a day. The SoC team provided all the physical information required for RealTime Explorer and were able to perform RTL exploration on the sub-blocks which had congestion during placement and routing. RealTime Explorer ran in less than one hour and the engineers were able to quickly analyze the routing congestion map produced by RealTime Explorer, which identified the same routing congestion hot-spots as their ASIC services company’s placement and routing runs. The engineers were excited to see that the RealTime Explorer cross-probing and debugging capability could pin-point the exact RTL constructs causing their routing congestion, in this case a 1024 bit wide mux implementation. The engineers quickly modified their RTL and re-ran RealTime Explorer and were able to verify that the routing congestion had been eliminated before handoff to their ASIC services company.
In summary, the SoC team was able to run physically-aware RTL exploration on their sub-blocks and top-level within two days, analyze the routing congestion hot spots using the physical-to-schematic-to-logical cross-probing capability available in RealTime Explorer, refine their RTL code, re-run RTL exploration, and produce a netlist which was routing congestion free and met top-level timing closure. Upon conclusion of using RealTime Explorer, the engineers stated “With RealTime Explorer in our SoC design flow, we will save a minimum of six to eight weeks on our next design schedule”.