Provides Improved Timing, Power, and Area Results for SoC and ASIC Designs

Santa Clara, CA – March 19, 2013 — Oasys Design Systems announced today that register retiming capability for improved quality of results (QoR) is now available in the Oasys RealTime synthesis engine. The Oasys RealTime synthesis engine is the core technology of the Oasys RealTime Explorer and Designer products, the only EDA tools that produce the same implementation accurate results for RTL exploration and physically-aware synthesis.

“This new capability from Oasys is part of our ongoing commitment to our customers to provide the best possible QoR for SoC and ASIC design teams,” said Scott Seaton, President and CEO at Oasys. “By providing massive RTL capacity, up to 10 times faster runtimes, physical awareness, and now improved QoR, Oasys is empowering design teams to address the increasing demands of today’s SoCs and ASICs.”

Especially important in graphics, networking, and mobile applications, register retiming is a technique of moving the structural location of registers in a digital circuit to improve its performance, area, and power characteristics in such a way that preserves its functional behavior at its inputs and outputs. The RealTime synthesis engine automatically moves registers through combinational logic to balance and optimize the delay across each stage of a pipeline. RealTime synthesis provides an integrated equivalency checking capability that automatically verifies the retimed gate-level logic is correct functionally.  A key advantage of the retiming capability within the Oasys RealTime synthesis engine is that the results more accurately correlate to the results achieved after placement and routing because of its physically-aware synthesis capability.

“With the increased adoption of Oasys RealTime by SoC and ASIC designers worldwide, we are working with more and diverse customer applications.” said Paul van Besouw, Oasys CTO. “Register retiming capability is critical for SoC and ASIC designers who need to minimize power and area while simultaneously maximizing circuit performance.”

Register retiming is available immediately as a standard feature in the Oasys RealTime Explorer and Designer products.

OneSpin Equivalence Checking to be Bundled with Oasys RealTime Physical RTL Synthesis Software

MUNICH, GERMANY and SANTA CLARA, CALIF. –– February 26, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) and formal equivalence checking solutions, and Oasys Design Systems (www.oasys-ds.com), provider of Oasys RealTime physical register transfer level (RTL) exploration and synthesis software, today announced they have signed an original equipment manufacturer (OEM) agreement.

Under terms of the agreement, OneSpin is licensing a portion of its OneSpin 360™ EC technology, automated functional equivalence checking software, to Oasys to integrate with its RealTime Designer™ physical RTL synthesis software. More details on the flow integration will be announced by Oasys over the next several months.

“Oasys Design Systems is working on solving some of the most difficult IC design problems and making great strides,” says Dr. Raik Brinkmann, OneSpin Solutions’ president and chief executive officer (CEO). “We’re delighted to partner with Oasys, knowing that the OneSpin EC technology will be part of its solution. Design teams should be pleased with the result, improved user productivity and faster runtime.”

Scott Seaton, Oasys’ president and CEO, adds: “We have developed a close working relationship with OneSpin. Together, we are bundling equivalence checking with our next-generation physical RTL synthesis into an effective solution for a range of design environments.”

The OneSpin/Oasys partnership spans a number of years, beginning in 2010 when Oasys began using OneSpin 360 EC-ASIC during the development of RealTime Designer. OneSpin 360 EC-ASIC is being used for synthesis verification, comparing two representations of the same design before and after synthesis to ensure functional equivalence. Oasys enhanced the interface between the tools and demonstrated a compelling solution. A prototype is currently in beta development.

For more information, visit www.OneSpin-Solutions.com.

Santa Clara, CA – February 20, 2013 — Oasys Design Systems announced today the expansion of its international business presence with the addition of IncuSolution as its exclusive distributor in South Korea.  Oasys RealTime physical RTL synthesis tools are used by customers for both RTL exploration and physical implementation.  Oasys RealTime’s next generation architecture is helping customers get to market on time by eliminating time consuming iterations between front and back-end design teams.  Oasys RealTime has been adopted by many of the top semiconductor vendors and has been production proven at the 28nm process node.

“The newest tool from Oasys, RealTime Explorer, has drawn dramatic interest from SoC and ASIC development teams worldwide” said Scott Seaton, President and CEO at Oasys. “Our unique physical-to-logical cross probing capability is allowing SoC and ASIC engineers to quickly identify the root cause of timing and routing issues before RTL handoff for physical design, saving our customers on average about 2 months off their existing design schedules.  We are pleased to partner with IncuSolution as a solution provider to bring Oasys RealTime to the South Korean market.”

“Korean customers rely on strong local technical support and business relations,” said Min-Hee Son, IncuSolution COO. “IncuSolution is proud to partner with Oasys to provide our Korean customers with the personalized sales and support they require to maximize their success with EDA products.”

About Oasys Design Systems
Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new synthesis platform called RealTime, a fundamental shift in how RTL synthesis is used to design and implement today’s SoCs and ASICs. Corporate headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com.

RealTime, RealTime Designer and RealTime Explorer are trademarks of Oasys Design Systems. All other trademarks and registered trademarks are the property of their respective owners.

About IncuSolution Co., Ltd

IncuSolution Co., Ltd is a leading EDA distributor and solution provider with highly skilled engineers providing EDA tool sales & services to customers throughout South Korea.  The company is located at 10 Sindo Bldg 2F, Garakbon-dong, Songpa-gu, Seoul, Korea, 138-800.

Oasys RealTime Explorer Bridges Logical and Physical IP for Improved QoR

Santa Clara, CA – January 29, 2013 — Oasys Design Systems announced today that it has joined the TSMC Soft-IP Alliance Program to enable TSMC IP partners with a new RTL exploration tool to improve quality of results and reduce the iterations required for design closure.  RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling with new QoR and time to market issues. The introduction of RealTime Explorer by Oasys enables RTL engineers to have a physically aware, implementation accurate synthesis tool for top-level PPA and routing analysis without requiring them to be physical design experts.

The TSMC Soft IP Alliance program is an extension of TSMC’s IP Alliance program that allows Soft-IP partners to access and leverage TSMC’s advanced process technologies to optimize power, performance, and area for their IP. TSMC offers a large catalog of ecosystem-partner and RTL-based Soft-IP. Provider cores are checked through the TSMC foundry checklist to ensure the best possible design experience, easiest design reuse, and the fastest integration into the overall design system.

“The complexity and size of today’s soft IP blocks have created huge bottlenecks in synthesis runtimes – sometimes requiring many days to check the result of a single change to the RTL ,” said Paul van Besouw, Oasys founder and CTO. “Further, RTL engineers moving to 28nm nodes and beyond have struggled because of the lack of physical awareness within their traditional synthesis tools. The Oasys RealTime engine optimizes at a higher level of abstraction, allowing RTL engineers to change and check their RTL in hours not days.”

“We welcome the new RTL exploration capability provided by Oasys Design addressing IP complexity,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “The logical-to-physical cross probing capability that promises quick analysis of the root cause of timing and routing issues before handoff for physical design could have a profound time-to-market impact for our IP partners.”

About Oasys Design Systems
Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new synthesis platform called RealTime, a fundamental shift in how RTL synthesis is used to design and implement today’s SoCs and ASICs. Corporate headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com.

RealTime, RealTime Designer and RealTime Explorer are trademarks of Oasys Design Systems. All other trademarks and registered trademarks are the property of their respective owners.

 Santa Clara, CA – January 15, 2013 — Oasys Design Systems, providers of a revolutionary new platform for RTL synthesis that empowers RTL engineers, announced today that orders more than doubled in 2012 by the addition of several of the top semiconductor and IP vendors to its previous list of marquee customers. Oasys orders increased at an accelerated rate throughout 2012 as companies designing SoCs and ASICs continued to transition to advanced process nodes and novel device structures such as FinFETs, further stressing the capacity of their existing, traditional block-level synthesis tools. Oasys ended 2012 with a cash flow positive fourth quarter that sets the stage for continued growth in momentum in 2013.

“RTL engineers are realizing that the RTL handoff design flow at 28 nm and below requires using a physically aware synthesis tool with greatly increased design capacity to avoid unexpected iterations late in the design cycle that delays their time to market,” said Scott Seaton, Oasys President and CEO. “The Oasys RealTime synthesis engine optimizes at a higher level of abstraction, providing massive synthesis capacity and breakthrough runtime performance for today’s complex SoC and ASIC designs. RealTime synthesis was production proven in 2012 at the 28nm node by several customers and we’re now working closely with them, and our new customers, on 20nm and 14nm RTL design flows.”

Oasys recently introduced a new RTL exploration tool, RealTime Explorer, allowing RTL engineers to quickly and accurately identify top-level timing, power, area, and routing issues in their RTL before handoff to physical design teams. No other synthesis vendor offers the capacity to optimize the top-level of today’s complex designs that literally contain 100s of millions of gates, in one synthesis run. Oasys customers have demonstrated that with the Oasys high capacity and physically aware synthesis tool, unexpected iterations that delay design closure can be avoided.

RealTime Explorer is built upon the identical synthesis engine as the Oasys RealTime Designer tool that was introduced in 2009. For the first time, RTL engineers are guaranteed that the results they see during RTL exploration are exactly the same results that can be implemented by their physical design teams. “Our customers are taking advantage of the unique logical-to-physical cross probing capability of the unified RealTime database to resolve top-level timing and routing issues early in the design cycle – with the confidence of knowing the results will be achievable in a single iteration during the critical placement and routing process,” said Paul van Besouw, CTO and founder of Oasys.

About Oasys Design Systems Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new synthesis platform called RealTime, a fundamental shift in how RTL synthesis is used to design and implement today’s SoCs and ASICs. Corporate headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com.

RealTime, RealTime Designer and RealTime Explorer are trademarks of Oasys Design Systems. All other trademarks and registered trademarks are the property of their respective owners.

The Industry’s First Physical RTL Synthesis Tool for RTL Engineers

Santa Clara, CA – January 8, 2013 — Oasys Design Systems announced today the immediate availability of a new product called RealTime Explorer that empowers RTL engineers to quickly identify and resolve timing, power, area, and routing congestion issues early in the design cycle. RealTime Explorer is built upon the production proven RealTime synthesis engine inside RealTime Designer that has been adopted by many of the top semiconductor companies worldwide. Oasys is the only EDA vendor that has identical synthesis and optimization engines for RTL exploration and implementation, guaranteeing accuracy and correlation between front-end and back-end design teams. Oasys empowers RTL engineers by providing a single, integrated physical synthesis platform that allows RTL engineers to accurately identify and resolve top-level timing and routability without relying on physical design groups.

“RTL engineers have been restricted in their ability to optimize their designs because of the limitations of traditional RTL synthesis tools. By leveraging the massive capacity and breakthrough performance of the RealTime synthesis engine, RealTime Explorer allows RTL engineers to change and check their complex RTL code in hours not days.” said Paul van Besouw, Oasys founder and CTO.   ”RealTime Explorer’s ability to cross probe between physical and RTL databases allows RTL engineers to quickly and accurately identify the root cause of timing and congestion issues, enabling them to resolve these issues early in the design cycle. Oasys is the first company to provide all the design views an RTL engineer requires – from logical to physical – in a single RTL synthesis platform.”

RealTime Explorer was developed to eliminate design iterations between front and back-end design groups late in the design cycle and thus reduce time-to-market and improve quality of results (QoR). “Our customers are designing the highest performance and most complex SoCs and ASICs, and with RealTime Explorer they have been able to get their products to market faster and with better performance”, said Scott Seaton, Oasys President and CEO. “The addition of RealTime Explorer to their RTL design methodology has allowed our customers to reduce their time to design closure by 1 to 2 months over their previous methods”.

About Oasys Design Systems
Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new synthesis platform called RealTime, a fundamental shift in how RTL synthesis is used to design and implement today’s SoCs and ASICs. Corporate headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com.

RealTime, RealTime Designer and RealTime Explorer are trademarks of Oasys Design Systems. All other trademarks and registered trademarks are the property of their respective owners.

EDA Industry Veteran Scott Seaton Chosen to Lead Company into Next Phase

Santa Clara, CA – December 11, 2012 — Oasys Design Systems, the chip synthesis company, announced today that industry veteran Scott Seaton has been named the company’s President and CEO. Mr. Seaton was also appointed a director of the company. Mr. Seaton succeeds founder Paul van Besouw who will become the company’s CTO and Chairman of its board of directors.

“Oasys RealTime Designer’s massive RTL capacity and breakthrough performance enables optimization at the top level of today’s most complex designs which allows designers to find timing, power, area, and routability problems before physical design. The result is a dramatic reduction in design iterations for design closure, providing important time-to-market savings over existing synthesis tools that are limited to block-level optimization. Oasys RealTime Designer is in production use at several of the top 10 semiconductor firms and our customers have successfully taped out designs at the 28nm process node,” said van Besouw.   ”Scott’s extensive EDA business experience taking start-up companies to the next level will help Oasys scale and lead us into our next phase of growth.”

Mr. Seaton is an EDA veteran with more than 30 years of experience in sales, marketing and executive management.  Most recently Mr. Seaton was VP of Sales and Marketing at Carbon Design Systems where he helped transform the company into a market leader in system level design.  Previously, Mr. Seaton was the VP of Worldwide Sales at Enkoo, an SSL VPN networking appliance company that was acquired by Sonicwall.  Earlier Mr. Seaton was President and CEO of LIstenpoint, a venture-backed enterprise software company.   Mr. Seaton began his EDA career as VP of Channel Sales at Viewlogic.

“I am excited about the dramatic value in time-to-market savings our customers are seeing with Oasys RealTime Designer over their existing RTL synthesis tools,” stated Mr. Seaton. “As Moore’s law continues to enable ever more complex designs, customers are finding that their existing RTL design flows, built upon RTL synthesis technology that was architected 25 years ago, can no longer solve their timing, power, area, and routability problems. This creates a great opportunity for Oasys to leverage its breakthrough optimization and physical synthesis technology.”

About Oasys Design Systems
Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how RTL synthesis is used to design and implement today’s SoCs and ASICs. Corporate Headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855- 8537. Email: info@oasys-ds.com. For more information, visit: www.oasys-ds.com.

Gabe Moretti’s post-DAC newsletter hit the net last week including Paul’s retrospective on how DAC was for Oasys (well, it was certainly right here, right now). It is now online on Gabe’s website too.

Our first-ever floor demos showing why Chip Synthesis is a fundamental shift in how synthesis is applied to the design and implementation of ICs were well attended all three days and the feedback positive. The demo highlights the benefits of RealTime Designer, the first design tool for physical RTL synthesis of 100-million gate designs. It produces better results in a fraction of the time needed by traditional logic synthesis products through a unique RTL placement approach that eliminates unending design closure iterations between synthesis and layout.

Oasys RealTime Designer has once again made it onto Gary Smith’s list of what to see at DAC. As he says in his commentary:

Oasys continues to stick to their guns. Now that we have a SVP, and the resulting RTL Sign- Off point, more and more of the design will be handed off to Logic Synthesis with a Don’t Touch command. That means that Design Compiler’s superior optimization capabilities become less valuable than a synthesizer that can handle large designs. That doesn’t mean Design Compiler isn’t needed earlier in the design process, however today earlier often translates to the work being done by the IP vendor. This has given Oasys an opening that few suspected and they are taking advantage of it.

You can download the whole report and the list of companies here (pdf).

John Cooley has published his Cheesy Must See List for DAC 2012. Oasys is there again in the synthesis category.

Like last year (but with new $6 M in Series B funding) Oasys RealTime takes your RTL and floorplan to placed-gates “10X to 60X faster than Synopsys DC-Graphical can.”  Verilog, VHDL, System Verilog, MCMM synthesis, DFT, UPF/CPF low power design.  “Now we’ve done 28 nm tape-outs!”

He also speculates on what is under the hood in Xilinx’s Vivado:

Xilinx is chatting up its new Vivado Design Suite at this DAC, which I’ve heard is a combination of AutoESL (which they bought for $25 M back in early 2011) for SystemC/C/C++ synthesis, and Oasys RealTime (which they helped with $6 M financing) for Verilog/VHDL synthesis down to placed-FPGA-gates.