Oasys’ technology has the potential to positively impact the design flow for VLSI chip implementation. This is a new way of thinking for next-generation chip design implementation.
We have evaluated Oasys Realtime and, on a 1.5M-instance block, we saw a 48-minute runtime with production-worthy quality of result. This kind of runtime performance is necessary moving forward to tackle the coming design challenges.
RealTime Designer is not just an incremental improvement, it is truly the next generation of physical synthesis for complex, multi-million gate designs at leading-edge process nodes.
We just taped out our first 45nm design using RealTime Designer. The advantages are clear– the speed at which we can now run our largest complex blocks and the tightly correlated P&R results for our timing critical 28nm designs.
Xilinx has licensed Oasys technology and achieved excellent results across a wide range of designs.
RealTime Designer offers high-quality results and performs very well in our environment. It is a great tool that fits a very real performance need in today’s EDA market