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	<description>Real Time Designer</description>
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		<title>Customer Case Study:  Eliminating Lengthy Schedule Delays When Outsourcing SoC and ASIC Physical Design</title>
		<link>http://www.oasys-ds.com/customer-case-study-eliminating-lengthy-schedule-delays-when-outsourcing-soc-and-asic-physical-design/</link>
		<comments>http://www.oasys-ds.com/customer-case-study-eliminating-lengthy-schedule-delays-when-outsourcing-soc-and-asic-physical-design/#comments</comments>
		<pubDate>Tue, 19 Mar 2013 20:49:28 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[Blog]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1563</guid>
		<description><![CDATA[Shankar Vellanthurai, Director of Field Applications Engineering, Oasys Design Systems Recently Oasys was working with engineers at a networking company that produces SoCs for their routers. This SoC design team hands off a Verilog netlist to an ASIC services company for chip finishing once their RTL has been verified and synthesized. The SoC team had [...]]]></description>
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		<title>Oasys Design Systems Announces Register Retiming Capability</title>
		<link>http://www.oasys-ds.com/oasys-design-systems-announces-register-retiming-capability/</link>
		<comments>http://www.oasys-ds.com/oasys-design-systems-announces-register-retiming-capability/#comments</comments>
		<pubDate>Tue, 19 Mar 2013 15:37:46 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1559</guid>
		<description><![CDATA[Provides Improved Timing, Power, and Area Results for SoC and ASIC Designs Santa Clara, CA – March 19, 2013 &#8212; Oasys Design Systems announced today that register retiming capability for improved quality of results (QoR) is now available in the Oasys RealTime synthesis engine. The Oasys RealTime synthesis engine is the core technology of the [...]]]></description>
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		<title>OneSpin Solutions, Oasys Design Systems Ink OEM Agreement</title>
		<link>http://www.oasys-ds.com/onespin-solutions-oasys-design-systems-ink-oem-agreement/</link>
		<comments>http://www.oasys-ds.com/onespin-solutions-oasys-design-systems-ink-oem-agreement/#comments</comments>
		<pubDate>Sat, 09 Mar 2013 01:11:04 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1555</guid>
		<description><![CDATA[OneSpin Equivalence Checking to be Bundled with Oasys RealTime Physical RTL Synthesis Software MUNICH, GERMANY and SANTA CLARA, CALIF. –– February 26, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) and formal equivalence checking solutions, and Oasys Design Systems (www.oasys-ds.com), provider of Oasys RealTime physical register transfer level (RTL) exploration and [...]]]></description>
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		<title>Oasys Design Systems Expands into South Korea</title>
		<link>http://www.oasys-ds.com/oasys-design-systems-expands-into-south-korea/</link>
		<comments>http://www.oasys-ds.com/oasys-design-systems-expands-into-south-korea/#comments</comments>
		<pubDate>Wed, 27 Feb 2013 17:16:47 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1535</guid>
		<description><![CDATA[Santa Clara, CA – February 20, 2013 &#8212; Oasys Design Systems announced today the expansion of its international business presence with the addition of IncuSolution as its exclusive distributor in South Korea.  Oasys RealTime physical RTL synthesis tools are used by customers for both RTL exploration and physical implementation.  Oasys RealTime’s next generation architecture is [...]]]></description>
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		<title>Customer Case Study:  Identifying and Resolving Top-Level Timing Issues Early in the Design Cycle</title>
		<link>http://www.oasys-ds.com/customer-case-study-identifying-and-resolving-top-level-timing-issues-early-in-the-design-cycle/</link>
		<comments>http://www.oasys-ds.com/customer-case-study-identifying-and-resolving-top-level-timing-issues-early-in-the-design-cycle/#comments</comments>
		<pubDate>Wed, 27 Feb 2013 03:15:05 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[Blog]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1531</guid>
		<description><![CDATA[Shankar Vellanthurai, Director of Field Applications Engineering, Oasys Design Systems Recently I was helping one of our semiconductor customers who designs wireless connectivity solutions. The problem they were having is that the top-level timing of their complex SoCs was not available to verify until all the sub-blocks were assembled and placed by the back-end physical [...]]]></description>
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		<title>Got Routing Problems?</title>
		<link>http://www.oasys-ds.com/p1506/</link>
		<comments>http://www.oasys-ds.com/p1506/#comments</comments>
		<pubDate>Thu, 07 Feb 2013 22:43:28 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[Blog]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1506</guid>
		<description><![CDATA[Dan Ganousis, Vice President, Oasys Design Systems As design complexity increases, more and more design teams are faced with a new challenge – routing congestion. Complicating matters, the majority of most SoC and ASIC design effort today consist of assembling large IP blocks and design teams thus have very little understanding and visibility into the [...]]]></description>
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		<title>Customer Case Study: Identifying Congestion Early in the Design Cycle</title>
		<link>http://www.oasys-ds.com/customer-case-study-identifying-congestion-early-in-the-design-cycle-2/</link>
		<comments>http://www.oasys-ds.com/customer-case-study-identifying-congestion-early-in-the-design-cycle-2/#comments</comments>
		<pubDate>Thu, 07 Feb 2013 18:11:55 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[Blog]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1489</guid>
		<description><![CDATA[Ganesh Venkataramani, Applications Engineer, Oasys Design Systems Recently I was at a semiconductor company which makes IC’s for mobile phones.  The problem they were trying to solve was that in their previous tapeout they had run into congestion issues late in the physical implementation process and ultimately had to grow the floorplan size in order [...]]]></description>
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		<title>Oasys Design Systems Joins the TSMC Soft-IP Alliance Program</title>
		<link>http://www.oasys-ds.com/oasys-design-systems-joins-the-tsmc-soft-ip-alliance-program/</link>
		<comments>http://www.oasys-ds.com/oasys-design-systems-joins-the-tsmc-soft-ip-alliance-program/#comments</comments>
		<pubDate>Tue, 29 Jan 2013 14:06:36 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1454</guid>
		<description><![CDATA[Oasys RealTime Explorer Bridges Logical and Physical IP for Improved QoR &#160; Santa Clara, CA – January 29, 2013 &#8212; Oasys Design Systems announced today that it has joined the TSMC Soft-IP Alliance Program to enable TSMC IP partners with a new RTL exploration tool to improve quality of results and reduce the iterations required [...]]]></description>
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		<title>Oasys Design Systems Has Breakout Year In 2012!</title>
		<link>http://www.oasys-ds.com/press-release-january-15-2013/</link>
		<comments>http://www.oasys-ds.com/press-release-january-15-2013/#comments</comments>
		<pubDate>Wed, 16 Jan 2013 20:05:51 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1448</guid>
		<description><![CDATA[ Santa Clara, CA – January 15, 2013 &#8212; Oasys Design Systems, providers of a revolutionary new platform for RTL synthesis that empowers RTL engineers, announced today that orders more than doubled in 2012 by the addition of several of the top semiconductor and IP vendors to its previous list of marquee customers. Oasys orders increased [...]]]></description>
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		<slash:comments>0</slash:comments>
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		<title>Oasys Design Systems Launches RealTime Explorer</title>
		<link>http://www.oasys-ds.com/oasys-design-systems-launches-realtime-explorer/</link>
		<comments>http://www.oasys-ds.com/oasys-design-systems-launches-realtime-explorer/#comments</comments>
		<pubDate>Wed, 09 Jan 2013 17:46:31 +0000</pubDate>
		<dc:creator>oasys-admin</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.oasys-ds.com/?p=1432</guid>
		<description><![CDATA[The Industry’s First Physical RTL Synthesis Tool for RTL Engineers Santa Clara, CA – January 8, 2013 &#8212; Oasys Design Systems announced today the immediate availability of a new product called RealTime Explorer that empowers RTL engineers to quickly identify and resolve timing, power, area, and routing congestion issues early in the design cycle. RealTime [...]]]></description>
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