Gabe on EDA has a piece about the new power capabilities of Oasys RealTime Designer.

RealTime Designer follows a “Place First” methodology that takes RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement it until chip-level constraints are met.