RealTime Designer from Oasys Design Systems

Synthesizes 100-million-gate Chips in Single Run

Chip Synthesis Takes Complete Chip from RTL to Placed Gates

Santa Clara, California — Oasys Design Systems today took the wraps off RealTime Designer™, the first design tool for physical RTL synthesis of 100-million-gate designs, synthesizing RTL to placed gates in a single pass and in a fraction of the time compared to traditional synthesis. RealTime Designer features a unique RTL placement approach that eliminates unending design closure and iterations between synthesis and layout. RealTime Designer is already in use in production flows at leading-edge semiconductor and systems companies worldwide.

"At Renesas, we are planning to expand the use of RealTime Designer in both our customer SoC flow, as well as for our own LSI designs," said Yoshio Inoue, Chief Engineer of Design Technology Division, Renesas Technology Corp. “Predictable results and a convergent flow through layout are critical to get to market on time. It was our appreciation that RealTime Designer produces better results than competitive tools and in a fraction of the time. This kind of performance is revolutionary. We are very impressed with the breakthrough technology from Oasys.”

Current flows inefficient

Traditional logic synthesis is running out of steam on designs of 20 million gates or larger. Design teams must sacrifice quality of results by optimizing for run time with smaller blocks or deal with agonizingly long run times with larger blocks, resulting in sub-optimum design flows designed around the limitations of current logic synthesis solutions. In current design flows, the synthesis is done a block at a time and without the context of the chip’s floorplan. This approach typically leads to numerous iterations between synthesis and layout and suboptimal results in layout.

RealTime Designer Offers a Breakthrough Solution

RealTime Designer follows a “Place First” methodology that takes the RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement until the chip-level constraints are met.

Design teams must manually check for many results, such as design congestion, and send the design repeatedly through synthesis and layout. RealTime Designer is the first product to automate that process. Designers can give RealTime Designer the chip floorplan as input or, if no floorplan exists then Oasys will create a floorplan including macro, pin and I/O placement. At completion RealTime Designer produces a placed design and a netlist that meets the constraints in the context of the desired floorplan.

Real-life Results

Synthesizing a physical block using TSMC 65nm – 700k instances, 70 Macros, running at 600MHz, and a "golden" floorplan – RealTime Designer completed the task in just 20 minutes and achieving design closure after a single iteration in place and route. In the traditional approach on the same design, a single iteration of synthesis took 14 hours. Furthermore, it took 6 months of iterations to achieve the best result of -300ps Worst Negative Slack, and in the end was not able to achieve design closure.

Real Time Designer takes in standard inputs, including Verilog, standard timing and physical libraries, SDC timing constraints, and floorplan. VHDL will be available later this year. Output has been tested through all the popular place and route systems.

Price and availability

RealTime Designer is immediately available and pricing begins at $395,000 for a one-year time-based license.

About Oasys Design Systems

Oasys Design Systems is a privately funded company providing Chip Synthesis technology, a fundamental shift in how synthesis is applied to the design and implementation of IC’s larger than 20 million gates. The company has attracted the support of legendary EDA leadership and its products are in use at leading edge semiconductor and systems companies worldwide. For more information visit the website at http://www.oasys-ds.com

Media Contacts:

Oasys Design Systems, Inc.
Sanjiv Kaul
408-855-8531