Oasys Design Systems Adds VHDL Support to RealTime Designer

Latest Release of Chip Synthesis Software Includes Multi-Mode Feature

 

SANTA CLARA, CALIF. –– November 17, 2009 — Oasys Design Systems announced today announced that it has added support for hardware description language VHDL and multi-mode capabilities to its RealTime Designer™, the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs. 

“Project teams use VHDL for the design of some of the most complex communications chips imaginable, which is why support for this language was an imperative,” remarks Paul van Besouw, Oasys’ president and chief executive officer.  “We are pleased to deliver well-tested and robust VHDL support and multi-mode synthesis in RealTime Designer.”

RealTime Designer’s multi–mode feature, the ability to synthesize RTL code in multiple modes, offers design teams a way to synthesize their designs to support both functional and test modes.  They can specify specific constraints for different modes and ensure that the design will run correctly in all desired modes.

Oasys has created a new EDA product category called Chip Synthesis™, a fundamental shift in how synthesis is applied to the design and implementation of integrated circuits (ICs).  Its RealTime Designer synthesizes RTL code to placed gates in a single pass and in a fraction of the time traditional synthesis does.  A unique RTL placement feature eliminates unending design closure and iterations between synthesis and layout. 

RealTime Designer follows a “Place First” methodology that takes RTL code, partitions it into blocks, places the RTL code in the context of a floorplan and implements each block all the way to placement.  Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results.  During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement until the chip-level constraints are met.

In addition to VHDL, RealTime Designer accepts Verilog, along with standard timing and physical libraries, SDC timing constraints and floorplans.

Earlier versions of RealTime Designer are already in use in production flows at leading-edge semiconductor and systems companies worldwide.

Availability and Pricing

RealTime Designer Version 9.3 is shipping now.  It is priced from $395,000 (U.S.) for a one-year, time-based license.

About Oasys Design Systems

Oasys Design Systems is a privately funded electronic design automation (EDA) with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates.  It has attracted the support of legendary EDA leaders and its RealTime Designer™ is in use at leading-edge semiconductor and systems companies worldwide.  Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif.  95054.  Telephone:  (408) 855-8531.  Facsimile:  (408) 855-8537.  Email:  info@oasys-ds.com.  For more information, visit:  www.oasys-ds.com

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RealTime Designer and Chip Synthesis are trademarks of Oasys Design Systems.  All other trademarks and registered trademarks are the property of their respective owners.

 

NEWS RELEASE

 

For more information, contact:

Sanjiv Kaul                                                 Nanette Collins

Oasys Design Systems                                Public Relations for Oasys Design Systems

(408) 855-8531                                         (617) 437-1822

sanjiv@oasys-ds.com                                 nanette@nvc.com