John Cooley has published his Cheesy Must See List for DAC 2012. Oasys is there again in the synthesis category.
Like last year (but with new $6 M in Series B funding) Oasys RealTime takes your RTL and floorplan to placed-gates “10X to 60X faster than Synopsys DC-Graphical can.” Verilog, VHDL, System Verilog, MCMM synthesis, DFT, UPF/CPF low power design. “Now we’ve done 28 nm tape-outs!”
He also speculates on what is under the hood in Xilinx’s Vivado:
Xilinx is chatting up its new Vivado Design Suite at this DAC, which I’ve heard is a combination of AutoESL (which they bought for $25 M back in early 2011) for SystemC/C/C++ synthesis, and Oasys RealTime (which they helped with $6 M financing) for Verilog/VHDL synthesis down to placed-FPGA-gates.