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(r)EvolutionInnovation in RTL Synthesis Technology

The Oasys RealTime engine is a revolutionary advancement in the state of the art of RTL synthesis technology. Traditional RTL synthesis tools optimize at the gate-level, which for the past 25 years has provided adequate design capacity and synthesis runtimes. As design complexity has grown however, traditional synthesis tools are now a major limitation for SoC/ASIC teams as they mandate partitioning at the block-level. The inability of SoC/ASIC teams to optimize at the top-level, consuming their entire design in one synthesis and optimization run, is the root cause of unexpected design iterations and thus delays in design closure.

The RealTime synthesis engine is different. By optimizing at the RT level instead of the gate-level, RealTime provides SoC/ASIC teams a synthesis tool with massive design capacity and breakthrough runtime performance. SoC/ASIC teams are now able to quickly identify timing, power, area, and routability issues at the top-level of their designs before handoff to back-end physical design teams – an extremely important capability for today’s complex designs that is not possible with any traditional RTL synthesis tool.

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RealTime is also a physical RTL synthesis tool – another innovative capability for SoC/ASIC teams. RealTime optimizes all the way from RTL to placed-gates using a novel “Placement First” methodology. SoC/ASIC teams are now able to not only optimize for timing, power, and area – but also for routability issues like congestion. Combined with the massive capacity and runtime acceleration enabled by RealTime’s higher level of optimization abstraction, RealTime allows SoC/ASIC teams to visualize the physical results of their RTL designs. This unique capability ensures when RTL is handed off to the physical design team, no routability issues will be found late in the design cycle.

RealTime produces a floorplan in addition to an optimized gate-level netlist … a revolutionary new capability for SoC/ASIC teams that is changing the way companies design today’s complex SoCs, ASICs, and complex IP blocks. Placed gates within an optimized floorplan accelerates the physical design process – RealTime users report a 6-8x runtime improvement in physical design because of the “guidance” provided to place and route tools. Time is critical and RealTime saves design teams lots of it.

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