Oasys RealTime Designer brings a new approach to design creation, taking an entire chip design all the way from RTL down to placed gates/macros in a single pass. The physical RTL synthesis approach is so efficient that designs of tens of millions of gates can be handled on an off-the-shelf PC in a few hours, producing results as good as or better than the well-known mainstream synthesis tools take days to achieve. Final place and route is done with any standard commercial tool and correlates with the predicted performance.

Such an enormous increase in productivity is not just a number, it affects the way we view design methodology, just as a plane is not just a faster bicycle, it affects the way we view distance. Synthesis this powerful forms a new category, chip synthesis, delivering the capability to reduce an entire chip to placed gates in a very short period of time.

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