How does it work?
Oasys RealTime Designer reads in the entire design, along with the floorplan. If there is no floorplan, often the case early in the design process, then one is generated automatically. High-level modules in the input RTL are assigned to regions if constrained by the floorplan, and then the whole RTL is partitioned, already using this coarse placement information in timing and congestion analysis. In a modern process, any timing value without an associated route is little more than a guess so it is very important to have a physical location for every element before calculating any timing.Hard macros—larger blocks that will not be implemented using standard cells—are also provisionally placed so that they can be considered from both a physical obstruction and a timing point of view. If there is physical hierarchy in the design, then this is honored. RTL partitions are correctly assigned to be within the physical boundaries of the appropriate partitions.
At all times a fully detailed netlist of each RTL partition is available and is used to accurately time the design. This is the first breakthrough technology.
Next, to optimize the design and meet the design constraints, rather than starting to directly operate on these gates, the original RTL partitions are re-synthesized given their current physical and timing constraints. This fast constraint driven synthesis of RTL directly to library cells is the second breakthrough technology.
On top of that the RTL partitions themselves will get merged, repartitioned and replaced in order to meet timing constraints and reduce any congestion. In a final refine step all gates get a legal placement. Since the final placement already avoids excessive routing congestion, it should not subsequently get badly perturbed by the place and route tool.
The design and the placement are all fed forward to the place and route tool. The placement is so self-consistent that the place and route tool runs faster than normal, another productivity gain, and the timing resulting from the final detailed routing with all the parasitics included will be very close to the predictions from the front end.
The third breakthrough technology that powers RealTime Designer is the extremely efficient memory representation, which allows enormous designs to be handled with just a modest memory footprint.
Qualitative change
Being able to synthesize entire chips in a matter of a few hours, as opposed to taking days to synthesize the chip in separate blocks, is more than just a straightforward increase in productivity, it lets the designer focus on the design and not the limitations of the design tool.
Breaking the design into blocks that don’t correspond to the physical hierarchy is a recipe for trouble. It is very difficult to get a good partition, and hard to budget time constraints across the blocks and their associated multiple synthesis runs. Worse, the problems don’t really show up until after place and route, when the blocks that were separated only due to tool limitations must be put back together into blocks that match the physical hierarchy. Even with a physical hierarchy, it is better to synthesize the design as a whole to avoid having to create time budgets for each block when there isn’t enough information to do so well.
The other major qualitative change is a result of the enormously faster run-times. Very fast run-times provide a sort of currency that can be used to purchase two things. The obvious one is to purchase a shorter design schedule. Often, however, this will not be possible since the master schedule will be driven by other considerations. If the master schedule cannot be changed then the faster run-times can be used to buy a better solution, allowing time to experiment with higher level architectural tradeoffs that a traditional methodology ensures must be cast in concrete at the very start of the design, and lived with even if they turn out to be suboptimal.
For designs using Electronic System Level (ESL) tools, Oasys RealTime Designer is the missing link in the methodology. ESL tools all have an extremely coarse view of implementation tradeoffs. Traditional synthesis is just too slow to use at this early point in the design cycle when fast iteration is important. Oasys RealTime Designer gives both speed and accuracy making ESL methodologies practical for a much wider range of design types.
Power
In the future, Oasys will provide full support for the CPF and UPF power standards with support for voltage islands, automatic insertion of level-shifters, isolators and so forth.
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