Some details
Oasys RealTime Designer is in full production release.Input is in Verilog 2001 (for the design), SDC (for timing constraints), LEF (for physical library data), .lib (for library timing data) and DEF (for floorplan information).
Output is in the form of a Verilog gate-level (and macro) placed netlist, in Verilog and DEF, which can be read immediately into physical design for place and route using Cadence, Synopsys, Magma or other tools.
VHDL input will be in beta in Q3 of 2009. Support for CPF and UPF power formats will also be incrementally introduced in future releases.
